I was born in 13rd of December, 1976 in Doneck. Right here I finished school, trade college by specialization of cook. After that, I entered to the Doneck National Technical University on faculty of Computer Science. I like studing and therefore time in University passed insensibly.

In the spring of 2002, I passed testing, which organized Aldec Inc., and I was choosed for passing of probation period in Alatek company. This branch office located in wonderful town Krakow, the history who is very old. Working in team of really professionals, I took as knowledge in FPGA/ASIC area, as and work in team.

Passing probation period and befor diplom ractical work (7 month), I studied and fastened knowledge about languages of HDL-programming Verilog and VHDL. I was study process of designing this projects, which defined some devices for synthesis, implementation and writing to FPGA chip. I was learn work with Linux и Unix, script language Tcl/Tk, which is very popular in CAD system now. Acquainted and learned with HES (Hardware Embedded Simulation) for fast modeling of desings.

So, further my plans after studing linked with work in this company. And further future of world high technology connected, as it seem to me, with utilization FPGA technology, which gives to project and to instill in same place at the same time.