Chapter 11

 

MODEL-BASED ANALOG AND

MIXED-SIGNAL TEST

 

“Research in analog and mixed-signal (AMS) test has been strongly influenced

by the advances in digital IC test techniques and algorithms.

. . . However, digital test is still far more advanced than is AMS IC

test. The primary reason is the absence of a widely accepted paradigm

for analog and mixed-signal circuit test.”

 

— Bapiraju Vinnakota and Ramesh Harjani [699].

At present, there are relatively few CAD tools to assist in analog test design, so

this is usually done by hand. A frequent problem is that the functional analog tests

produced manually are not effective for manufacturing test of the IC on the available

tester, so the tests must be redesigned, again by hand. The cost of analog testers is

determined by the number of digital pins required for the tester, and by the number

of analog instruments added to the tester for analog testing. Functional digital signal

processing (DSP) based test sets are quite large in prototype testing. Also, with 22bit

analog-to-digital converters (ADCs) appearing, a standard histogram test for

this converter would require a huge number of tests and a very long test time to

collect sufficient samples for statistical analysis [621]. So, advances in analog and

mixed-signal test are needed to lower costs [699]. This chapter on structural analog

circuit testing requires an understanding of matrix algebra and the methods for

representing systems of partial differential equations as Jacobian matrices [61, 203].

 

History. Early analog test efforts began in the 1960s. Analog circuits usually

are tested functionally against their specifications, since they have few inputs and

outputs and relatively few devices. Test inputs are generated from the specifications.

Test application is expensive, however, because the number of specifications is large.

Early research focused on discrete analog circuits [699]. Since these components were

often unreliable, many failed during operation, and analog diagnosis was essential

to be able to repair defective circuits.

 

With the advent of mixed-signal ICs, the observability of the analog circuit

 

 

 Chapter 11. MODEL-BASED ANALOG AND MIXED-SIGNAL TEST

 

portions has been significantly reduced, when they feed on-chip ADCs. Conversely,

the controllability of analog circuit portions has also been significantly reduced,

when they are driven from on-chip digital circuits. The conventional DSP-based

approach to analog circuits is still favored by industry. Recently, there is evidence

that manufacturers only switch from separate digital and linear ICs to a mixed-signal

chip when forced to by cost competition. However, one can expect competition to

continually increase in microelectronics. System-on-a-chip (SOC) devices provide

a level of integration well beyond traditional mixed-signal devices. Putting entire

systems on a chip should eventually reduce I/O ports even further, thus reducing

the observability of increasingly complex circuits. For example, there are recent

efforts to put entire cell phones and personal computers on a single IC. This will

lead to very low pin count devices, which would have I/O for antenna, keypad,

display, microphone, speaker, and battery. At present, we do not know how to test

the increased number of internal components with just those inputs and outputs!

 

11.1 Analog Testing Difficulties

Fault Modeling Problems. The major difference between analog structural test

and analog functional test is the fault derivation and modeling procedure [621].

Functional test often assumes that the components are faulty and generates the

fault list using component deviations and catastrophic faults (see Section 10.1.)

Structural test uses manufacturing defect statistics, and the fault list may be either

catastrophic or parametric.

 

Analog circuits have complex relations between input and output signals. Many

analog circuits are non-linear systems (e.g., the MOSFET transistor, used as an

amplifier.) The circuit parameter values vary widely, even in good circuits. Deterministic

models are inefficient for analog circuits. Therefore, signals are specified by

a nominal value, along with an acceptable range of values around the nominal value.

Simulation and measurement inaccuracies and IC manufacturing process variations

determine the acceptable signal value tolerances [699]. Finally, statistical distributions

of analog faults generally are not known with enough precision to accurately

predict fault coverages of a test set. Soma [620] reports evidence of analog circuits

with catastrophic faults passing a conventional manufacturing test.

 

Simulation Error. Expected analog circuit signal values are computed by simulation,

whose accuracy is limited by the numerical accuracy of the simulation algorithm,

the simulation assumptions, and by the accuracy of the models of the

parasitic analog devices. Also, process variations cause even good circuits to exhibit

a range of different behaviors.

 

Tester Measurement Error. Measurement errors at the analog circuit tester come

from analog offsets, the effect of the load of the measurement probe on the analog

circuit behavior, and the impedance of the analog probe. Also, random noise is a

problem, so analog testers are limited in bandwidth and measurement accuracy [699].

 

 

11.2 Analog Fault Models

For mixed-signal chips, transporting internal analog signals to output pins may alter

the signal and the circuit functionality. Capacitive coupling between high-frequency

digital signals and analog signals causes additional analog circuit noise. Analog tests

must create a difference in an analog output between the good and bad machines that

lies outside the measurement error of the test fixture and the ATE [621]. Otherwise,

the fault effect is masked by measurement error.

 

Test Accessibility Problems. Circuit complexity and the inaccessibility of internal

components restrict the use of conventional analog ATE.

 

Manufacturing Process Variations. The various device parameters in large volume

manufactured integrated circuits follow statistical distributions. These process

variations can significantly impact component parameter values [699]. Analog design

and circuit layout techniques exist to minimize the effect of temperature and

diffusion gradients in circuit layouts. A parametric fault refers to component value

variations. However, the analog testing literature also refers to output parameter

variations, for example the variation in an amplifier gain. Both uses are correct, and

the meaning will be clear from the context. For analog devices, multiple parametric

faults (involving several minor component variations) are just as or more significant

than large single parameter variations or catastrophic faults.

 

Information Flow. It is difficult to test circuits by individually testing subcircuits.

Consider the case of two cascaded single-input, single-output analog circuits,

 

 

and

 

 

with analog voltage transfer functions H1 and H2.

and

may behave

unacceptably when tested individually, due to manufacturing imperfections that

distort their transfer functions. However, when cascaded, it could happen that the

distortion in H1 is cancelled by the distortion in H2, which might be, in some sense,

the inverse of the distortion in H1. Therefore, the cascaded combination of

 

 

and

 

 

may actually be acceptable. Conversely, individually acceptable analog circuits,

 

 

when cascaded, may produce an unacceptable circuit.

 

11.2 Analog Fault Models

The conventional fault models for analog circuits are catastrophic or hard faults,

where an analog component becomes open or shorted, and the parametric or

 

 soft

faults, where an analog R, L, C, or transistor trans-conductance

 

 

value changes sufficiently that it moves outside its tolerance box and causes unacceptable

performance degradation of the analog circuit. Sometimes the addi

 

 

tional faults stuck-at-

 

 

and stuck-at-

 

 

are also included in the catastrophic

 

faults [699]. Catastrophic faults are easy to test, and parametric faults are difficult

to test.

 

Single parametric faults are interesting in multi-chip module interconnects, as

they will be termination resistances or important components such as precision offchip

inductors used in RF circuits. Linear analog ICs are designed so that the analog

 

 

 Chapter 11. MODEL-BASED ANALOG AND MIXED-SIGNAL TEST

 

 

Figure 11.1: Amplification circuit.

 

 

 

Figure 11.2: Compensated OPAMP circuit.

 

performance depends on ratios of components, so multiple parametric faults are most

interesting in such chips. Many analog circuits are designed using Block’s negative

feedback principle, where an OPAMP is configured with an input impedance and

a feedback impedance. Generally, it is the ratio of these two impedances that determine

whether the OPAMP circuit is an integrator, a differentiator, or a buffer.

Therefore, a multiple parametric fault model is the most useful fault model in this

situation. Figure 11.1 [275, 276] shows an amplification circuit where the first ampli

 

 

fication stage comprises

 

 

and the first OPAMP, the second stage is a high-pass

 

filter comprising

 

 

and

and the final stage is a low-pass filter comprising

and the second OPAMP. The functional parameters of interest during test

 

 

are shown in Table 11.1. Only two of these are single parametric faults, and the

remaining ones are multiple parametric faults. However, we are not interested in all

multiple parametric faults. The total number of double parametric faults is

and the total number of triple parametric faults in this circuit is

 

Testing

all of these possibilities is expensive and unnecessary. Figure 11.2 shows a fully compensated

OPAMP, and the relevant transistor-level faults are listed in Table 11.1.

 

In DSP-based analog testing methods (see Chapter 10), no analog fault models

 

 

11.3 Levels of Abstraction

are used. In this chapter, the above fault models are used, and tests are generated

for specific multiple faults. At present, the structural testing methods are gaining

acceptance as a supplement to the DSP-based methods, but DSP-based methods

remain the most important.

 

11.3 Levels of Abstraction

It is useful in analog circuit testing, as in digital testing, to look at the circuit

from various different views. For analog testing, the transistor level of abstraction

provides detailed models and structural interconnections for analog devices. At this

level, the SPICE netlist, complete with transistor models, provides a structural view.

The system of non-linear partial differential equations describing the netlist provides

a behavioral view.

 

However, analog circuit testing can be done at a higher level of abstraction,

the functional level, in which we model resistors, capacitors, inductors, and ideal

OPAMPs, which have infinite gain and are considered to be fault-free. The benefits

of this higher level of abstraction are modeling convenience and computational efficiency,

and the liability is that OPAMPs may have faults, which should be tested for.

At the functional level, the structural view of the circuit is provided by a signal flow

graph, which graphically represents the idealized system of equations. Alternatively,

a behavioral view is provided by the network transfer functions.

 

11.4 Types of Analog Testing

Specifications. Each class of analog circuits (A/D converters, D/A converters,

filters, phase-locked loops, etc.) has its own separate set of specifications [699].

For each circuit class, there already exist accepted and specific functional tests for

 

 

 Chapter 11. MODEL-BASED ANALOG AND MIXED-SIGNAL TEST

 

prototype test, and smaller test sets for production test [699]. There is no universal

set of performance specifications. Also, there are no general design techniques for

all analog circuits.

 

Analog circuit tests can be classified into these three categories:

 

• Design characterization, to determine whether the design meets specifications.

• Diagnostics, which determine the cause of a device failure when it fails a test.

• Production tests used for large volumes of linear or mixed-signal circuits.

We will focus on fault-model based analog circuit tests. At present, functional analog

circuit testing without a particular fault model still reigns supreme, but it is now

being augmented by fault-model based analog circuit tests.

 

There is a further taxonomy of analog tests. Specification-based tests are generated

directly from the circuit specifications, without reference to an analog fault

model. This approach is easily adapted to wide varieties of circuits. However, with

large numbers of specifications, test application has become most expensive, and

its cost must be reduced. The test set can be reduced by locating dependencies

between specifications and eliminating unnecessary testing. Structural fault-model

based tests will target a specific set of modeled faults. This allows quantification of

a set of analog tests in terms of their fault coverage, so test sets can be graded [699].

The models also reduce the test set size, since test waveforms that detect faults already

covered by other waveforms can be deleted. However, advocates of structural

tests have been unable to establish a link between the fault coverage and satisfaction

of the design specifications [699]. This makes designers reluctant to accept

structural analog testing.

 

We will focus first on analog fault simulation, followed by automatic analog

test-pattern generation. For further information, consult Vinnakota’s book [699].

 

11.5 Analog Fault Simulation

Analog fault simulation is needed to evaluate the fault coverage, and effectiveness,

of a set of analog test waveforms, which may be manually or automatically

generated. Here we discuss three different kinds of analog fault simulation:

 

• DC fault simulation of non-linear circuits

• AC fault simulation of linear circuits

• Transient or time-domain fault simulation.

We first apply DC tests to analog circuits, and only if the circuit passes these do

we apply AC tests, which are more difficult to generate and more costly to apply.

Finally, only if the circuit passes AC testing do we apply transient or time-domain

tests.