ÿþ<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD><TITLE>>45;8 =59@>==KE A5B59 4;O @50;870F88 >B>1@065=89</TITLE> <META http-equiv=Content-Type content="text/html; charset=windows-1251"> <META content="MSHTML 6.00.2600.0" name=GENERATOR></HEAD> <BODY> <p>@838=0; <0B5@80;0 =0E>48BAO 745AL: <a href="http://www.analog.com/en/prod/0,,767_829_ADM560%2C00.html">http://www.analog.com/en/prod/0,,767_829_ADM560%2C00.html</a></p> <H1 align="center">APPLICATION HINTS LAYOUT</H1> <H4> AB@-22,25 <p> The AD7655 has very good immunity to noise on the power supplies. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD7655 should be designed so the analog and digital sections are separated and confined to certain areas of the board. </p> <p> This facilities the use of ground planes that can be separated easily. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7655, or as close as possible to the AD7655. If the AD7655 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7655. </p> <p>Avoid unning digital lines under the device because these couple noise onto the die. The analog ground plane should be allowed to run under the AD7655 to avoid noise coupling. Fast switching signals such as CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This reduces the effect of crosstalk through the board. The power supply lines to the AD7655 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply impedance presented to the AD7655 and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each power supply pin AVDD, DVDD, and OVDD close to, and ideally right up against these pins and their corresponding ground pins. Additionally, low ESR 10 ¼F capacitors should be located near the ADC to further reduce low frequency ripple. </p> <p>The DVDD supply of the AD7655 can be a separate supply or can come from the analog supply AVDD or the digital interface supply OVDD. When the system digital supply is noisy or when fast switching digital signals are present, if no separate supply is available, the user should connect DVDD to AVDD through an RC filter (see Figure 17) and the system supply to OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7655 has five ground pins: INGND, REFGND, AGND, DGND, and OGND. INGND is used to sense the analog input signal. REFGND senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. AGND is the ground to which most internal ADC analog signals are referenced; it must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. </p> SLAVE SERIAL INTERFACE External Clock The AD7655 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS . When both CS and RD are low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 31 and Figure 32 show the detailed timing diagrams of these methods. While the AD7655 is performing a bit decision, it is important that voltage transients do not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase of each channel, because the AD7655 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is provided, it is a discontinuous clock that is toggling only when BUSY is low or, more importantly, that it does not transition during the latter half of EOC high. External Discontinuous Clock Data Read After Convert Although the maximum throughput cannot be achieved in this mode, it is the most recommended of the serial slave modes. Figure 31 shows the detailed timing diagrams of this mode. After a conversion is complete, indicated by BUSY returning low, the conversion results can be read while both CS and RD are low. Data is shifted out from both channels MSB first, with 32 clock pulses, and is valid on both rising and falling edges of the clock. Among the advantages of using this mode is that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is the ability to read the data at any speed up to 40 MHz, which accommodates both slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7655 provides a daisy-chain feature using the RDC/SDIN (serial data in) input pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when it is desired, as in isolated multiconverter applications </H4> </BODY></HTML>