Research of structures of controlling automatic devices with elementarization linear sequences of states

Contents

1. Introduction

2. The purposes and tasks

3. Scientific novelty and practical value

4. Existing researches

5. Current and planned results on a theme

6. Summary

7. Literature

Introduction

Engineering process of any project can be divided into following stages: the analysis of requirements and the existing information, technical design, development of the program and testing.

The essence of technical design consists in writing the explaining text and a code, on the basis of the gathered data and requirements on a requirement specification. At a stage of writing of a code the system is realized for a target hardware-software platform according to a requirement specification. Testing should confirm correspondence of implementation of the project to requirements.

Semantic break of transmission of knowledge between stages of technical design and writing of a code consists that the developer realizes system in correspondence with the understanding of a requirement specification [1].

Already for a long time there is simulation language UML which fits operation of the programmer, helping it to divide structure of the program into the simplified structures and to present, as these structures will cooperate. UML it is represented useful and at designing. It will allow to standardize different representations about the same objects of modelled system.

There is one big disadvantage UML is a static picture, the drawing of model, «lifeless essence». Demand on "started" UML Recently grows, that designing on the basis of models (Model-Driven Design) has led to appearance of such direction in program engineering. The main idea of such approach is independent consideration of the models created at designing of system, from details of their implementation on a concrete hardware-software platform. Designing on the basis of models should lead to appearance of universal graphics programming languages [1].

From the aforesaid necessity of transferring of principles of development of software on development hardware follows.

The chips programmed by the user, have opened new page in history of modern microelectronics and computer facilities. Thereof an LSI/GSI, intended for solution of specialized tasks, standard production of electronic industry with all positive consequences following from it: mass production, deprecication of chips, periods of development and an output on the market of production on their basis.

At present there is a set of classes EPLD(FPGA), but following ИС are most often used: SPLD, CPLD, FPGA. [3]

Now one of vital topics is the theme of finite state automations. The finite state automation is represented with graph of states and transitions which describes how the described object reacts to obtaining of events. [2]

Link between the finite state automation and the hardware implementation of the automatic device is EPLD(FPGA).

Now growth of usage EPLD(FPGA) for implementation of automatic devices stops dearness of chips. Therefore designers-programmers should solve the task of decrease of the hardware expenses (in this case – square of a chip EPLD(FPGA) or number of valves) with greater expenses of time of development.

There is a set of methods to reduce the hardware expenses by usage of additional units (for example multiplexers, RPROM) which add to algorithm flexibility of the automatic device with programmed logic (DPL) and speed of the automatic device with hard logic (DHL).

Necessity of creation of a development environment of the hardware device which would be based on UML and MDA follows from the aforesaid, and also would consider existing optimization techniques of structure at generation of resultcode.

The purposes and tasks

The analysis modern element basis and existing methods of synthesis of controlling automatic devices on PLA(PLM), EPLD(FPGA) for definition of ways of decrease of cost of logic circuits;

Research of efficiency of the selected methods

Choice of development environment UML of the editor with support "started" UML

Testing of software product for convenience of the interface

Research of an overall performance of software product on minimization of hardware expenses for existing EPLD(FPGA).

Scientific novelty and practical value

It is planned to develop the software which would provide synthesis and development of circuits of managing directors and finite state automations, using existing high technologies, such as UML, HDL, FPGA and Java. Practical value of a product consists in methods of the approach to the designing, linked with new optimization techniques of structure of the automatic device, and also availability of a program code of a product and possibility of its modification.

Existing researches

Presence of editors FSM testifies to a urgency of a theme of finite state automations (finite state machine) in such products as AHDL and Riviera. The Most widespread among description languages of the equipment are languages VHDL and Verilog. However direct implementation of controlling automatic devices in these languages is labour-intensive process. Therefore the special tools have been included in structure of many foreign CAD, allowing to simplify development of controlling automatic devices. So FSM unit is included in structure of CAD Active-HDL of Aldec corporation. This unit possesses a multifunctional graphic interface, for the description of controlling automatic devices. However FSM unit possesses number of disadvantages. In particular, the form of record of the controlling automatic device demands knowledge of language HDL. Systems of designing of controlling automatic devices and in other CAD are In a similar way organized.

Also FSM models at code generation do not consider hardware expenses at generation result code as it will be necessary that it is made by resources of synthesis, but the generated code does not consider many features of implementation of structure of the automatic device, therefore resources of synthesis often produce not the most optimal configuration result devices.

Comparative results of parameters of the synthesized devices at the identical initial columns-schemes, realized by resources FSM A-HDL (finite state machine) and by means of the structural description result circuits, show the certain decrease of number of used units FPGA at implementation by the second way.

Results of synthesis (for COTTON VELVET Lattice ispGDX2 Part LX256V):

Disadvantage of FSM-editor A-HDL – generation of a program code in behavioural style that does impossible to predict result of synthesis. The structural description of the circuit received as a result of trivial implementation, enables predictions of results even before synthesis – at a stage of generation of a program code that enables to generate a code for a chip or numbers of valves FPGA of the set dimension. [4]

As to UML editors for finite state automations one of such developments is executed graphics language on the basis of SWITCH-technologies and UML-notations – UniMod which describes behaviour of the object by means of graphs of transitions of structural automatic devices with the notation, and columns of transitions are under construction by means of the notation of the diagram of states UML.

Package UniMod provides development and execution of the automaton-oriented programs. It allows to create and edit UML-diagrams of classes and states which correspond to the circuit of links and the graph of transitions, and supports two types of implementation — on the basis of interpretation and compilation. In the first case there is a possibility:

To transform diagrams to format XML;

To execute the received XML-description by means of the interpreter created on the basis of a set of developed base classes. These classes realize, for example, such functions as event processing, saving of a current state, recording.

In the second case of the diagram it will directly be transformed to a code in the target programming language which subsequently is compiled and started.

Designing of programs with usage of package UniMod assumes the following approach: the logic of the application is described by the structural finite state automation set in the form of a set specified above diagrams, constructed with usage of the UML-notation. Sources of events and objects of handle are set by a code in the target programming language. [1].

One of UML the editors allowing partially to realize a task in view, is Poseidon. It is convenient the interface and generates comprehensible result code, but its disadvantage that data program product has the paid license and the closed program code that does impossible its modification in a necessary direction.

To one more UML the editor is UMLet constructed a development team on the basis of platform Eclipse, development covers all UML, that is rather inconvenient for the given discussed theme.

Current and planned results on a theme

Necessity of program implementation of methods of generation of a structural code of columns-automatic devices and application of optimization of this code follows from the analysis of existing problems and requirements.

The software product should possess the set forth above advantages (generation of a structural code under the set graph, count of demanded square of a chip, etc.).

During the analysis of optimization techniques and the constant extension of their number there are certain requirements to implementation of software product, the certain structure is formed.

Picture 1 - Structure of a developed CAD

The developed system should consist of following parts:

The graphics editor who realizes possibility of graphics mapping, editings and creations demanded graph-scheme (FSM).

The compiler which enables a textual set of the graph and coercion of textual representation in internal language of the program (XML, XMI, etc.).

The generator of a code with various optimizers, which will transform an internal code of the graph in concrete (Moore or Mile) implementation of the automatic device. [4]

After implementation of software product will be carried out researches concerning efficiency of the generated code for various existing FPGA chips, schedules of dependences, and also results of integration of the program with various existing resources of synthesis will be constructed.

Picture 2 - Development of driving automaton

Summary

Result of operation will be the software constructed on platform Eclipse with an open code and realizing code generation in language HDL. The program code will be generated in view of existing algorithms of optimization of controlling automatic devices and EPLD(FPGA) is specified under concrete. Input parameters will be a UML circuit of implementation of the controlling automatic device.

At a writing of the given author's abstract master's work is not completed yet. Final end: January, 2007. The full text of work and all materials on a theme can be received at the author or its head after the specified date.

Literature

1)  Гуров В.С., Мазин М.А., Нарвский А.С., Шалыто А.А. UniMod: метод и средство разработки реактивных объектно-ориентированных программ с явным выделением состояний // МЕТОДЫ И СРЕДСТВА ОБРАБОТКИ ИНФОРМАЦИИ. – Московский государственный университет им. М.В. Ломоносова, М. – 2005. – С 361-366.

2) Ю.Г. Карпов Теория автоматов. – С-Пб., Питер, 2002. – 206 с.

3) Е.А. Суворова, Ю.Е. Шейнин Проектирование цифровых систем на VHDL . – С-Пб., БХВ-Петербург, 2003. – 560 с.

4)  Бережок А.Ю. Система автоматического проектирования в среде A - HDL устройств, представленных конечными автоматами // Інформатика та комп'ютерні технології – ДонНТУ, Донецк – 2005

5) Часть 1. Технический обзор Платформы Eclipse – http://khpi-iip.mipk.kharkiv.edu/library/extent/prog/ETO/I.html

6)  Зеленева И.Я. – «Методы синтеза многоуровневых структур управляющих автоматов на программируемых логических устройствах» – диссертационная работа.