NOC-SYSTEMS

1. NOC-systems overview

With the growth of the number of SOC components it is necessary to revalue the design technology and architecture. And next step of SOC evolution should be development of network-on-chip (NOC) projects.

A System-on-chip (SOC) combines several processing elements into a single silicon chip. The present reality of VLSI projects in market is differentiated by small time-to-market, high complexity and high performance. While the time-to-market is very important, complexity and performance cannot be committed; otherwise it may reach the market with a product that is neither feasible nor competitive. The use of cores (prefabricated modules) is one way to reduce the complexity of current digital systems. Often, these components are technological products, software and knowledge that are subject to patents and costs of intellectual propriety (IP). Thus the digital system will contain some cores that will implement complex functions. One strategy to reduce design time and therefore meet time-to-market requirements is through the use of reusable core or Intellectual Property (IP).

In the future, SOCs will have dozens or even hundreds of processing elements. According to the International Technology Roadmap this will grow to 4 billion transistors running at 10 GHz. Such benefits as system performance improvements, reductions in costs, size and power dissipations and reduced design turn-around-time can be achieved through the use of SOCs. Therefore, on-chip communication architectures will need to be scalable due to the need of interconnecting a greater number of on-chip components into network processors and other SOCs. On the other hand implementing and organizing all the processing elements of a SOC as a single processor with many functional units is not convenient (it is difficult to extract large amounts of instruction level parallelism –ILP- from a single instruction stream).

Future SOCs need to overcome the limiting factor of on-chip interconnections:

• physical constraints (which reduces functional unit utilization and slows down

inter-communication);

• limited bandwidth inter-resource;

• inefficient synchronization schemes;

• access-pattern-dependent throughput;

• inability to hide the latency of the internal network;

• poor parallel-computing models and

• energy consumption.

Thus designers to project future chips have to find the appropriate design and process technologies, as well as the ability to interconnect the existing components – including processors, controllers, and memory arrays - providing the functionally correct and reliable operations conducive to the proper interaction of the components.

This communication emphasizes the importance of a new SOC design approach, the NOC.

2. The Approach to Networks

To consider a SOC as a micro-network, with a group of interconnected processing elements amongst themselves, allows the use of techniques and design tools used in generic networks facilitating the design of the complex SOCs. Table 1 shows the difference between a micro-network and a general network.

The network is the abstraction of the communication between components and must satisfy quality-of-service requirements—such as reliability, performance, and energy limits— under the limitation of intrinsically defective signal transmission and considerable communication delays on wires.

Network on a chip schemes came to solve future SOC architectural and design productivity issues. These issues are overcome through the capability of a NOC to provide a regular connection network connecting multiple resources and standardizing the management of various inter-resources communications needs. Other significant motivations for the NOC schemes are: reusability of existing IP blocks, physical-architectural-level design integration, and platform-based design methodology.

Benini and Micheli propose using the micro network stack paradigm, an adaptation of the protocol stack to abstract the electrical, logic, and functional properties of the interconnection scheme. Every layer is specialized and optimized for the target application domain in a vertical design flow.

3. Interconnection Network’s Topology

The physical layer specifies the connection wire links. It must transmit a signal without errors and with a low level of energy consumption satisfying competing quality metrics and making available a complete abstraction for the micro-network layers above.

Figure 1 – Direct network.

Direct and Indirect Network: in a direct or point-to-point network (see Figure 1) each node directly connects to a limited number of neighbouring nodes. This architecture overcomes the scalability problems of shared-medium networks. In indirect or switch-based networks a connection between nodes must go through a set of switches. The network adapter associated with each node connects to a switch’s port.

Hybrid Networks: two examples are multiple-back-plane and hierarchical buses. These architectures cluster tightly coupled computational units with high communications bandwidth and provide lower bandwidth intercluster communications links. 

4. Micro-Network Control

The protocols specify how to use the network resources during system operation. Network control dynamically manages network resources during system operation, striving to provide the required quality of service.

Data Link Layer: the physical layer is an unreliable digital link in which the probability of bit upsets is non-null. Data-link protocols increase the reliability of the link, up to a minimum required level, under the assumption that the physical layer by itself is not sufficiently reliable. It defines error detection and correction protocols in packet communications. The packet size and the number of outstanding packets can be adjusted in this level seeking maximum performance with a low probability of residual error, within energy consumption constraints.

Network Layer: this layer implements end-to-end delivery control. Routing algorithms establish the path a message follows through the network to its final destination. Deterministic routing algorithms are best suited for identical or regular traffic patterns providing the same path between a given source destination pair. In contrast, adaptive approaches use information regarding network traffic and channel conditions to avoid congested network regions. This approach is preferable when dealing with irregular traffic or in networks with unreliable nodes and links.

Transport Layer: above the network layer, the transport layer decomposes messages packets at the source, re-sequences and reassembles the messages at the destination. Packetization granularity presents a critical design decision because most network-control algorithms are highly sensitive to packet size. Packet standardization constraints can be relaxed in SOC micro-networks, which can be adapted at design time. In general, either deterministic or statistical procedures will offer the basis for flow control and negotiation.