Master's thesis

Myadelets Oleksandr

Theme of master's thesis:

"Development and research of method of synthesis of tests for typical elements of replacement"

Author: O. Myadelets
Tutor: к.т.н.Y.Е. Zinchenko

e-mail:    san.san@mail.ru

Content

The work actuality


The synthesis of the digital equipment tests is one of the classical tasks of electronic computing technique (ECT) diagnosis, radioelectronic and electronic-computing apparatus. But, despite this it remains practically unsolved. It can be explained first of all by different rates of diagnosis theory development and progress of ECT. Lately there has appeared a new direction – design for testability (DT), the main characteristic of which is the testing functions that are put in it on the stage of equipment projecting. This in its turn provides the lowering of the labour-consuming character while diagnosis ware elaboration and first and foremost while test synthesis. In present time the diagnosticians and chief electronic computing technique producers pay this direction primary attention, thus in this sphere one can observe considerable progress, both in theoretical and practical sense.

On the other side, in CIS countries (cooperation of independent states), including Ukraine, the ECT park on the industrial and defensive enterprises is characterized by the dominance of old technologies. The acquisition of modern systems with selftesting functions remains an unsolved problem, mainly because of economical reasons. That’s why the subject of this master work is directed at elaboration of the digital typical elements of substitution of synthesis tests system.

One of the directions of making tests is called accidental (pseudoaccidental) testing, which provides rather quick construction of the testing system. But it has one disadvantage – the low tests plenitude of the complicated objects of diagnosis (OD). That’s why the decision was made to choose the determined test synthesis, which provides high tests plenitude, though it is more slow. The main efforts in this work are directed at eliminating of this very defect.

The survey of existing methods


All the variety of diagnosis methods can be distinguished by the following features:

  1. according to the way of inlet influence generation;
  2. according to the way of output reactions analysis;
  3. according to the suitableness of the object of diagnosis;
  4. according to the way of finding (localization of) the defects.

According to the way of inlet influence generation the testing can be:

  1. comprehensive;
  2. casual;
  3. pseudocasual;
  4. determined;
  5. combined.

The detailed testing means the sorting out of the existing inlet influence.

The pseudocasual tests – are the casual choice of inlet influence. If the pseudocasual sequences are used for providing of the choice of all the existing inlet vectors, except the null vector, it means that such testing is pseudoexhaustive.

The determined testing takes place on the inlet sequences with the strictly regulated order of vector movement. Such sequences need regular methods of synthesis. One distinguishes the following methods of determined tests synthesis:

  1. structural;
  2. functional;
  3. structurally-functional approach.

Structural methods are based on the detailed description of OD. Such method allows to synthesize the test for every ECT, though it is rather labour-consuming.

The functional method is based on the testing of OD functions. It is a so-called "black box", its structure is absolutely unknown. The functional testing is factually exhaustive; it has a disadvantage – the abundance of tests.

The alternative of the listed methods is the structurally-functional approach, which implies the testing of ECT functions, taking into consideration its structural peculiarities. Still, its labour-consuming nature is rather high.

The analysis of the test reactions is carried out by comparing the information acquired and the standard information, which can be received either from the physical standard equipment or from its logic model.

The list of the tasks, solved in the present work


The aim of the present paper is the elaboration of the method, which provides the optimal rise of the determined test generation effectiveness. For the realization of the given aim the following tasks are solved:

  1. The analysis and the classification of the defects.
  2. The analysis of the structures and means of determined test vectors generation.
  3. The elaboration and the increase of well-known methods of determined test generation effectiveness

Personal elaborations


We plan to work out and test the determined test generation method, which uses the results of pseudocasual test generation. This method has to provide the high completeness of the test and little time, needed for test generation. To get the practical results we plan to realize one of the methods of test synthesis, using the C++ programming language.

Experimental research


To analyze the worked out methods ISCAS'85 is used. ISCAS'85 is a combination of the so-called standard (Benchmark circuit) logic schemes that were worked up by the leading scientists-diagnosticians who aimed at estimating the test synthesis quality with the help of different diagnostic systems.

The task of the experimental researches is to prove the high effectiveness of the methods under consideration in comparison with their analogues, using the standard ISCAS'85 schemes.

The survey of the results. Conclusions


At the present moment the main theoretical information about synthesis of digital equipment tests is studied and systematized; the OrCad possibilities are analyzed; the methods of automatized construction of determined tests are scrutinized; the application, carrying into effect the automatized generation of the determined tests is being planned to be worked out.

The carried out work adduced the necessary theoretical scientific proof for the qualitative implementation of the masterwork.

Bibliography


  1. Agrawal V.D. Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Kluwer Academic Publishers, 2000, - 690c.
  2. Peattie C.G.. Elements of Semiconductor Device Reliability. Proc. IEEE, vol. 62, 149-168, Feb. 1974.
  3. Colboume E.D., G.P. Coverly, and S. K. Behera. Reliability of MOS LSI Circuits. Proc. IEEE, vol. 62, pp. 244-259, Feb. 1974.
  4. Schnable G.L., L.G. Gallace, and H.J. Pujol. Reliability of CMOS Integrated Circuits. Computer, vol. II, pp. 6-17, Oct. 1978.
  5. Rosenberg S. J.. H-MOS Reliability. IEEE Trans. Electron Devices, vol. ED-26, no. I, p. 48, Jan. 1979.
  6. Digital Failure Rate Data Book. 1981, Rome Air Development Center, MDR-17.
  7. Готра З.Ю., Николаев Н.М. Контроль качества и надежность микросхем. М.: Радио и связь, 1989.,168с.
  8. J. Bateson. In-Circuit Testing. New York: Van Nostrand Reinhold Company, 1985.
  9. E.A. Amerasekera and D.S. Campbell. Failure Mechanisms in Semiconductor Devices. Chichester, UK: John Wiley & Sons, Inc., 1987.
  10. L.C. Wang and M.S. Abadir. Test Generation Based on High-Level Assertion Spec-ification for PowerPC™ Microprocessor Embedded Arrays. Journal of Electronic Testing: Theory and Applications, vol. 13, pp. 121-135, Oct. 1998.
  11. Горяшко А.П. Синтез диагностируемых схем вычислительных устройств. М.: Наука., 1987. – 288 с.
  12. Мангир Т.Э. Источники отказов и повышение выхода годных СБИС. ТИИЭР. – 1984. – т. 72, № 6. – С. 35 – 56.
  13. Мурога С. Системное проектирование сверхбольших интегральных схем: Пер с англ. М.: Мир, 1985. – 288 с.
  14. M. Sachdev. Defect Oriented Testing for CMOS Analog and Digital Circuits. Boston: Kluwer Academic Publishers, 1998.
  15. G.R. Case. Analysis of Actual Fault Mechanisms in CMOS Logic Gates. in Proc of the 13th Design Automation Conf., June 1976, pp. 265-270.
  16. R.L. Wadsack. Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits. Bell System Technical Journal, vol. 57, no. 5, pp. 1449-1474, May-June 1978.
  17. M.K. Reddy, S.M. Reddy, P. Agrawal. Transistor Level Test Generation for MOS Circuits. in Proc. of the 22nd Design Automation Conf., June 1985, pp. 825-828.
  18. S.K. Jain and V.D. Agrawal. Modeling and Test Generation Algorithms for MOS Circuits. IEEE Trans on Computers, vol. C-34, no. 5, pp. 426-433, May 1985.
  19. D. Agrawal and S.C. Seth. Test Generation for VLSI Chips. IEEE Computer, Society Press, 1988.
  20. S.M. Reddy, M.K. Reddy, V. D. Agrawal. Robust Tests for Stuck-Open Faults in CMOS Combinational Logic Circuits. in Proc of the 14th International Fault-Tolerant Computing Symp. June 1984, pp. 44-49.
  21. P. Jalote. An Integrated Approach to Software Engineering. New York: Springer-Verlag, 1991.
  22. P.A. Thaker, V.D. Agrawal, M.E. Zaghloul. Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. in Proc. of the 17th VLSI Test Sump, Apr. 1999, pp. 182-188.
  23. L.C. Wang and M.S. Abadir. Test Generation Based on High-Level Assertion Specification for PowerPC™ Microprocessor Embedded Arrays. Journal of Electronic Testing: Theory and Applications, vol. 13, pp. 121-135, Oct. 1998.
  24. Y.K. Malaiya and R. Rajsuman. Bridging Faults and IDDQ Testing. Los Alamitos, California: IEEE Computer Society Press, 1992.

Up

Developed by Oleksandr Myadelets (June 2006)