Tolkachov Dmitriy

Faculty: Computer Science
Speciality: Computer Systems and Networks

Theme of master's work:

Development and research of managing automat of Mealy with the reshaper of address in the base of CPLD.

Scientific adviser: Zelenyova Irina

Abstract of the masters work

Introduction

РThe development of microelectronics and the widespread use of its products in industrial production, especially in control systems by a variety of objects and processes is currently one of the main directions of scientific - technical progress. Therefore, research in automatic control basis CPLD (which are used in mobile phones, communicators and other mobile technology) will help to optimize the hardware cost, and consequently reduce the size and cost of devices.
The principle of control allows the firmware to use modern digital technology, the digital device consists of two parts: an operating automata (OA) and control automata (CA). In operating the device are performed arithmetic and logical operations, as the nodes of the operating device comprises: registers, counters, adders, decoder and other. Managing automat (MA,same CA) forms a sequence of control characters in the OA, under the influence of OA by implementing more sophisticated algorithms. Such a sequence of operations known as firmware, and are usually written in the form of a graph scheme of algorithm. MA divided into broad groups: machines with rigid logic and machines with programmable logic. In turn, the machine with a rigid logic into machines made under the scheme Mealy or Moore. In machines with rigid logic diagram automaton is uniquely interprets circuit graph firmware.
In this work will be performed:
1. Analysis of the functioning of MA Mealy from the address driver.
2. Investigation of the possible optimization of the structure of the machine.
3. Development of CAD on the synthesis of MA Mealy from shaper address.
4. Analysis of results.

Relevance

In connection with the dynamic market of digital electronics, such as rapidly growing market of software for the design of digital circuits. Also, many companies-developers (eg, Xilinx) provide opportunities for training with their software and hardware. Therefore, I believe that the creation of CAD (for synthesis, and training purposes) for the design of digital devices (controlling the machine in the basis of CPLD) - a demand work.

Relationship of academic programs, plans, themes.

Master's work is done during the years 2008-2009 under the scientific direction of the department «Computers» Donetsk National Technical University.

The purpose and objectives of development and research

The aim of this work: the goal is the creation of CAD, which automates the process of synthesizing MA Mealy from shaper address.
The main objectives of development and research:
1. To investigate the influence of parameters GAW (branching ratio, the length of successive linear relationships) for the space occupied by an automaton in the crystal.
2. Developing software shell, which is input in the form of graph-schemes of a given algorithm in the file format *. xml calculates the necessary parameters for the structural units of the machine.
3. The development of CAD, which is on the parameters calculated in Clause 2 creates behavioral model with automatic shaper address.
The subject of development and research: administering machines sold in the basis of CPLD.
Property development and research: CAD for the synthesis of MA Miles from shaper address.
Methodology and Methods: Using the basic provisions of a Boolean algebra, the theory of finite automata.

Scientific novelty

1. For the first time we investigated the dependence of the square of the crystal parameters of the machine GAW Mile with driver addresses. 2. For the first time developed a CAD system for the synthesis of HDL-model MA-Mile with driver the address in the basis of CPLD. 3. The first results of the CAD system tested on a standard PLIS - CoolRunner II XC2C256.

Practical significance

The practical importance of the development is the use of CAD for the synthesis of automatic control in the basis of CPLD, as well as the use of complex programs for other types of machines. This program can also be used for training purposes for the development of knowledge of the programmable logic integrated circuits and the theory of synthesis, as well as for training with scheme CoolRunner II XC2C256.

Testing of the work

The results were presented at the V all-ukranian scientific-technical conference of students, graduate students and young scientists «Комп’ютерний моніторинг та інформаційні технології» (КМІТ – 2009).

Review of research and development on theme

Local review: Kostyanok Tatyana "Development of methods for the synthesis of automatic firmware Mealy encoding object"
Yakubovsky Andrey “Research control automat with rigid logic to PLIS "
Vypritskaya Polina «Automating the synthesis of automatic control at Mile FPGA»
Berezhok Alexey «Investigation of the structures of Governors automata with linear sequences of states elementarization»
Maxim Danilov «Development and study of the automated design of composite controllers firmware»
Miroshkin Alexander «Synthesis and study of composite firmware control systems with the basic structure»
Lavrik, Alexander «Synthesis and study KMUU to retrofit the system to mikrokomand PLIS»
National review:
Kharkiv National University of Radioelectronics
Chair of Computer Aided Design Computer Technology

Sevastopol National Technical University
The department of cybernetics and computer technology

Odessa National University named after I.I. Mechnikov
Department of Computer and Information Technology.

Taurian National University. V.I. Vernandskogo. Physics Department The Department of Computer Engineering

Global overview:
St. Petersburg State University of Information Technologies, Mechanics and Optics
Chair «Technology Programming»

Institute of Informatics and Electronics, University Zelenogurskogo (Zielona Gora, Poland)

Novosibirsk State Technical University
Faculty of Automation and Computer Technology
The Department of Computer Engineering

Faculty of Computer Science Technical University of Dresden (Germany)

Moscow State Institute of Electronic Technology
Faculty of Electronics and Computer Technology
Department of Planning and Design of Integrated Circuits

Main part

In the introduction, justified the relevance of the topic of master work, formulated the goal and objectives of the work, the idea of work and its scientific novelty.
In the first part of review of existing programmable logic integrated circuits.
PLA has the most flexibility, as they would allow to realize the reduced DNF of BF, with the number of terms in each function can be arbitrary. PLA technology is the development of technologies and PROM first appeared in 1974. PLA consists of input and output buffers and programmable matrix «AND» and «OR»

Figure 1 - Structure of PLA

Currently, however, actually dropped out of the PLM and production have been replaced with other devices - CPLD (complex programmable logic devices).
CPLD architecture resembles the popular PAL (Programmable Array Logic) architecture, where logic resources and implemented an array of elements, combined elements or, in turn, institutions or directly to the trigger output. Such a simple logical structure is quite simple to understand, provides a very short time, compile and minimum delays pin-to-pin.

Figure 2 - Structure of CPLD

In the restructuring scheme, the following designations. Through the FB (FB) about the importance ¬ functional blocks, whose number N depends on the level of interest ¬ grace and chips varies quite widely. Each FB has a makroyacheek MN (MC, Macrocells). The functional blocks of the beam ¬ input signals from the programmable matrix compounds PMS, PIA, Programmable Inerconnect Array). The number of such signals t. Output signals FB comes in ICP, and in blocks of I / O CPLD (IOBs, Input / Output Blocks, HE). PIP provides a complete dial-up function blocks, ie the possibility to submit messages to any of their output to any input.
Block I / O associated with the findings of the external bi-directional I / O, which, depending on the programming can be used as entrances or exits. Three lower output, or to specialize in ¬ testimony for the matrix of functional blocks signals GCK (Global Clocks)-Global taktirovaniya, signal GSR (Global Set / Reset) global installation / reset signals and the GTS (Global 3-state Control) of global governance to the state of the output buffers, or the same conclusions can be used for input / output.
The number of contacts, I / O can match the number of exits of FB, but may be smaller. In the latter part of makroyacheek can only be used to develop internal signals of the device (in particular, the feedback signal). The need for such signals is typical of the structures of most digital devices.
CPLD different manufacturers and different complexity are functional ¬ functional blocks, in principle little different from each other in their architecture and composition of elements:

Figure3 - Functional Block

The main parts of the functional blocks are programmable CPLD ¬ ruemaya matrix elements and (MI), the matrix distribution terms of MRI and a group of several (N) makroyacheek. In essence, each FB represent ¬ ing another PAL-like structure with some differences from the options ¬ TOV used in the simple PLD (PML). As in the classical PLD, in the block has multiinput matrix MI generating kon ¬ yunktivnye terms for use in subsequent parts of the block.
The second part describes the basic structure of the studied machine, as well as the influence of parameters graph-schemes of algorithms in its structure.
The scheme administrator of the machine Mile shaper address is used to optimize the square crystal Plis by reducing the number of exits in comparison with the trivial implementation of MA Miles. Synthesis scheme begins with the encoded string direct structural table machine (STM). Then shall be converted ЫЕЬ - set Eh = (e1, e2 ... en) encodes the line number table. The next step is encoded a set of micro - a lot of output Y. A table of the excitation functions of memory and are encoded micro kits (mikrocommands) [1]. Functional scheme of the implementation of this algorithm consists of the following sites
-PLM - form code lines STM on the basis of input signals Xl and codes am.
-PZU1 - parallel forms memory functions and codes mikrocommands.
-PZU2 - forms the output of the state machine.

Animated picture - Work of PFY automata(pictures -4, cycle -6)
The third part will describe the process of developing a CAD program, as well as related modules
In the fourth part will describe the results of the CAD, as well as the comparative characteristics of synthesizing MA Miles from the address on the driver CPLD as to makroyacheek.

Conclusions

In the process of work were considered the most modern PLIS, as well as the selected base for the implementation of controlling the machine with Miles shaper address. A total of CA miles with driver addresses, as well as studies on the influence of parameters GAW square crystal, which is the machine.
Planned development of CAD, which is the input data (GAW format *. xml) forming HDL-administrator model of the machine, ready-to-synthesis for PLIS.

Literature

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