The performance of analogue phase-locked loops (PLLs) has steadily improved with operating frequencies extending to 8GHz and beyond. Recently, digital PLLs based on direct digital synthesis (DDS) have emerged as alternatives in certain applications.

So what are the differences between analogue PLLs and DDS-based digital PLLs, and how should the designer choose the best option.

A digital PLL implements traditional PLL building blocks using digital logic. While there are many ways to implement a digital PLL,the focus here is on DDS-based digital PLL architectures.

For example, a reference divider, which reduces the frequency of the incoming signal before it goes to the phase detector, is the same as that of an analogue PLL.

The reference divider setting plays a key role in PLL behaviour. If the designer must use a large reference divider and a low phase detector frequency to generate the desired output, the maximum loop bandwidth will be constrained.

In an analogue PLL the phase detector generates pump-up/pump-down current pulses, whose duration is proportional to the phase difference between the reference and feedback signal. In a digital PLL, however, the phase detector’s output is a digital number proportional to the time difference between the edges of the incoming reference signal and the feedback signal. These digital words are sent to the digital loop filter, which filters the phase detector output. Because the loop filter parameters are numerical coefficients, however, they can be easily changed. And unlike an analogue PLL, there is no practical limit to their size. In addition, the digital phase detector doesn’t suffer from thermal noise, aging or drift, and charge pump mismatch or leakage.

The reconstruction filter is one important component not found on an analogue PLL. This low-pass filter removes frequency content above the fundamental output frequency, leaving only the desired sine wave. A fifth- or seventh-order low-pass filter is common, depending on the filtering requirement and how close the output frequency is to the Nyquist frequency. This sine wave can then be fed into a fanout buffer to produce a square wave clock output.

Once we have an understanding of the component blocks used in a digital PLL, we can begin to realise some of its benefits.

First start, the digital PLL excels in frequency translation applications. For example, translating the common 19.44MHz networking clock frequency to 156.25MHz necessitates dividing the incoming signal by 1944, and running the phase detector at 10kHz. In order to maintain loop stability, the maximum PLL loop bandwidth is typically constrained to about 1/10 of the phase detector frequency, or 1kHz in this case.

Fractional-N PLLs can help by keeping the phase detector frequency high, but introduce problems of their own.

In an analogue PLL, low loop bandwidths require bulky loop filter components, which not only take up board space, but lead to self-resonance and microphonics when ceramic capacitors are used.

The digital PLL can also have a reference spur due to finite steps of phase correction, but this spur can be suppressed more easily because the digital loop filter makes it easy to implement very small loop bandwidths (less than 1Hz). More importantly, because the loop characteristics are determined by digital coefficients, the loop dynamics are much more tightly-controlled than in an analogue PLL.

Because the loop parameters are programmable in a digital PLL, the user can maintain the same loop transfer function for a variety of conditions. The loop filter can be optimised for constant loop bandwidth and phase margin for both cases. More importantly, the loop parameters can be adjusted by merely programming registers instead of changing components.

A DDS-based digital PLL has the advantage of a high-speed DAC system clock for reference monitoring. This clock can be used to oversample the reference inputs, and allows for detection of reference clock drift or failure. Once a failure is detected, the device can either automatically switch inputs or go into holdover mode. The stability of the output clock in holdover mode is the same as the stability of the system clock.

The presence of DAC spurs is a potential drawback to digital PLLs. A low-pass reconstruction filter is very effective in eliminating these. While it is possible to have higher-order DAC spurs at or below the desired output frequency, these spurs are often much lower (less than 70dBc) in amplitude. If the output frequency is close to the DAC Nyquist rate, the designer should be careful to choose a system clock frequency so that lower-order spurs are not close to the desired output frequency, thereby allowing them to be effectively filtered.

Choosing the correct DAC system clock is an important consideration when using a digital PLL. In the most demanding applications, a high-frequency oscillator can be used to provide the 800MHz to 1000MHz DAC system clock directly. However, few applications demand their performance.

Many digital PLLs feature an analogue PLL clock multiplier that produces phase noise numbers acceptable for many applications. In these cases, the designer can drive the DAC system clock PLL with a common 16MHz or 25MHz crystal, or with crystal oscillators in the 16MHz to 100MHz range, thus allowing the on-board PLL to generate a 1GHz system clock. In this case, the noise of the on-board PLL is the primary contributor to output jitter.

To overcome the limitations of either PLL design, it is possible to combine a digital PLL followed by an analogue PLL. The digital PLL can handle clock switching and difficult frequency ratios, while the analogue one can be used to further attenuate spurs, multiply to higher frequencies, and perform clock distribution.

So in systems where holdover, reference switching, and loop reconfiguration are not necessary, the analogue PLL presents an attractive option, and one that allows for higher output frequencies. On the other hand, the digital PLL excels in redundant clocking applications where smooth switching, holdover, and well-controlled loop dynamics are needed. Their flexibility and dynamic reconfiguration allow different frequencies on the reference inputs, and a DDS-based digital PLL handles low reference frequencies exceptionally well.