1. Introduction

Phase-locked loop (PLL) is a feedback loop which locks two waveforms with same frequency but shifted in phase. The funda¬mental use of this loop is in comparing frequencies of two waveforms and then adjusting the frequency of the waveform in the loop to equal the input waveform frequency. A block diagram of the PLL is shown in Figure 1. The heart of the PLL is a phase comparator which along with a voltage controlled oscillator (VCO), a filter and an amplifier forms the loop. If the two frequen¬cies are different the output of the phase comparator varies and changes the input to the VCO to make its output frequency equal to the input waveform frequency. The locking of the two frequencies is a nonlinear process but linear approximation can be used to analyze PLL dynamics.

In getting the PLL to lock the proper selection of the filter is essential and it needs some attention. If the filter design is understood from control theory point-of-view then the design becomes quite simple. In this short note we will discuss only the fundamentals of the PLL and how you can use nonlinear simulation and linearised approximation to get a better understanding of the PLL.

Figure 1: Basic Phase-Locked Loop

1.1. Multiplier as Phase Comparator

Modern PLLs have digital phase comparator but there are PLLs with analog phase comparators too. They are made up of a simple multiplier and a low-pass filter. The output of the multiplier is made up of two periodic waveforms—one has the frequency of the difference of the frequencies of the two input sinusoid and the other wave’s frequency is their sum. The former is obtained by passing the output of the multiplier through a low-pass filter.

Let the input to the multiplier be v_imsin(ω_it) and v_omcos(ω_ot + φ(t)) then the output voltage v_p is

This output v_p is passed through a low-pass filter and if the two frequencies ω_i and ω₀ are close together then the output of the filter is a function of the phase difference between the two input waveforms given by

The output v_olp is a function of the instantaneous phase difference (ω_it - (ω_ot + φ(t))) between the two waveforms.

1.2. The Locking Action

To understand the locking mechanism it’s best to do simulations and plot signals at different points in the loop. The simulation is discussed in Section 3. Here we give a plausible explanation of how the PLL locks.

Let’s look at the output of the low-pass filter v_olp (Figure 1) as given by equation (2) and consider that φ(t) = 0 and ω_i > ω₀. For a short while this will result in a positive value of v_olp. This positive value will increase the output frequency of the VCO bringing ω_i and ω₀ closer. Since the output v_olp is a sinusoid after its phase value exceeds 180 degrees ((ω_i - ω₀)t > π) things will go the wrong way around but since the difference between the two frequencies is lesser it will not pull the two frequencies as much apart as brought together during the time the phase was less than 180 degrees. This cycle will repeat and in every cycle the two frequencies will keep coming closer together and finally they will lock. A symmetrical cycle starting with a negative value for volp will pull the two frequencies together when ω_i < ω₀.

From equation (2) we see that if ω_i is equal to the free running VCO frequency then the output of the low-pass filter should be zero. This means φ(t) in equation (2) should be zero. What if the output of the VCO is vom sin(ω₀ + φ(t)) instead of the cos function as in equation (2)? Then for the PLL to lock when the input frequency is equal to the free running VCO frequency, the phase difference φ(t) between the two waves has to be 90 degrees. Why?

2. Linearised PLL

To analyse the behaviour of a PLL we can linearise it about the locking frequency obtained with zero input voltage to the VCO. This frequency is also known as free running frequency of the VCO. The linear model then only deals with the change in frequencies about this lock frequency.

The linear approximation to the PLL is shown in Figure 2. The block F(s) in Figure 2 is the low-pass filter to get a signal proportional to the difference in frequency (and phase) of the two waveforms. Looking from the phase comparator point-of-view, the output of the multiplier and low-pass filter is a signal equal to the sine of the phase difference between the two input signals. So our linear approximation is valid only when the phase difference is small.

Figure 2: Linear Phase-Locked Loop Block Diagram

To analyse the PLL in Figure 2, let’s write the transfer function

For

2.1. Lock Range

Let the VCO output frequency be ω₀ for zero input voltage. We need to know what is the range of input signal frequencies for which the output will lock and this range is called the lock range of the PLL.

To calculate the lock range we need to know the phase difference for which the phase comparator works. Some phase comparators work for only a 90 degree range and there are others which work for a full 360 degrees. Some PLL schemes do frequency dividing and thereby enable a comparison over very large phase range. For the digital phase comparator discussed later, the input phase range is 90 degrees. In this case the lock range is

This is the maximum frequency variation that can be had within the loop.

2.2. Filter Design

For a simple low-pass filter F(s), it can be seen that the second-order closed-loop system will have underdamped poles if K_DAK_o is large and ω₁ small. A quick root-locus sketch should clarify this point. We need large K_DAK_o for a large lock range but that makes the system underdamped. One solution is to have a zero in the filter F(s) which damps the system.

For practical reasons of attenuating the out of bandwidth signals, the cut-off frequency of the low-pass filter is kept as low as possible (this may vary with different applications). A low cut-off and a high K_DAK_o results in underdamped response which can be improved by using a compensating network as shown in the simulink implementation next.

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