Resume Abstract DonNTU Masters
Pavel Perkin
Українська Русский

Pavel Perkin

Faculty of computer science and technology (CST)

Department of computer engineering (CE)

Speciality Computer systems and networks (CS)

Master's theme: Research of structures of composite control devices using distributed computing

Scientific adviser: Candidate of Technological Science Zeleneva Irina

Research of structures of composite control devices using distributed computing

Abstract:

In the article the technique of using a multiprocessor computing resource when designing a large number of control devices. We propose a protocol of interaction of cluster nodes, the algorithms of scripts that implement the proposed protocol.

The general formulation of the problem

To implement the digital device is widely used basis for programmable logic integrated circuits (FPGA)[4]. Modern FPGA chips have the property of reconfigurable, which allows the end user to perform the design of digital devices using specialized CAD. The duration of the design process directly depends on the computing power of your PC. To increase the productivity of the design process can be performed using distributed computing [1]. At the same CAD system run this on multiple processors is difficult, but the execution of several independent processes simultaneously can significantly reduce overall design time.

The main idea of ​​the proposed method is the simultaneous execution of many processes in the synthesis of multiprocessor computing resources (cluster DonNTU NeClus) when designing a large number of control devices. The aim is to reduce design time, a large number of digital devices. To achieve the goal it is necessary to solve several tasks: to study especially the organization of the cluster to develop a communication protocol control unit with operating units, to develop and explore methods of balancing the load of operating units, to investigate the effectiveness of the use of multiprocessor computing resource for the mass execution of weakly coupled problems.

Design of the control unit can be divided into two stages: the synthesis model and its implementation in the respective elemental basis. For the synthesis of CU CAD models used, developed at the Department of Computer Engineering DonNTU. The initial data for the synthesis of a description of the flow-chart of the control algorithm in the format of XML. With the help of CAD models can get a lot of control devices, interpreting the original algorithm. The model is a vhd-files that describe the functional components of control devices, and mif-file containing the firmware (to control devices with memory). The model also contains a tcl-script that automates the implementation phase of the CAD Xilinx ISE [3]. Tcl-script sets the project name, the list of included files, type, and the family of basic FPGA chip, as well as additional options.

The second stage of designing the control unit is to implement the model in VHDL-FPGA chip basis using specialized CAD software Xilinx ISE [3]. The paper proposes a method of implementing a distributed set of models of control devices on a multiprocessor cluster NeClus. The scheme of interaction between the terminal and the cluster is shown in Fig. A.

Figure A. The scheme of interaction between the terminal and the cluster nodes

The technique of cluster comprises the following steps: - connection to the host-node cluster (in this case the terminal is any PC connected to the Internet, the connection is made on a protocol SSH) [2]; - input data for processing, which represent a set of files to models CU and scripts for automated execution of the process of implementation; - start implementing a distributed process; - waiting for the end of the process of designing and producing results.

The distribution process of the implementation of VHDL-models between nodes executes the script on the host-site. Rooms are available at the same set of nodes in a special file.

After transferring the archive to the models in the N-site handler runs a script that generates a list of tcl-scripts, each of which specifies a set of input parameters, such as family housing and FPGA timing parameters, etc. As the cluster nodes are equipped with a 4-core processors, expedient at one site simultaneously run up to four processes of implementation.

At the end of the implementation of the results generated, containing statistical data of chips, such as the number of hardware resources involved (LUT-elements and blocks of memory) and time parameters (time clock, time preset data signals, the formation time of the output functions). Removing the input archive is a sign of the end of the process of implementing a site-handler. Upon detection of this trait in the next survey of the site-site handler will give the manager the next input file and run the script processing. Managing a cluster node polls all nodes periodically handlers. Sampling frequency is chosen in such a way as to reduce the duration of idle nodes and processors do not upload unnecessarily management node. In practice, using a poll in a minute.

Archive with the results of implementation, the user can pick from the host-machine when you reconnect to the cluster.

Findings

Practical implementation of the proposed method has significantly reduced the time required for the design of a large number of digital control devices. Further studies aimed at developing methodology to balance the load of cluster nodes and, thus, a gain in time cost.

Important notice

In writing this abstract master's work is not yet complete. Final completion: December 2012. Full text of the work and materials on the subject may be obtained from the author or his scientific adviser after that date.


References