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Abstract

Content

Introduction

The design process of digital devices is a very long and hard task, which requires high skill level specialists. Thus, training is the most important aspect for any company in any field of activity, especially in developing various devices and software.

The modern world provides many ways for learning: schools, universities, specialized courses, etc. However, no matter how well it was taught the information, the most important process in studying is self-education. Beacause of that, today one of the most popular methods of learning is online learning.

There are many resources in the Internet that provide a variety of information as well as a set of tools, which people needs for the experiments. This is especially important for students of such areas as computer engineering, because they need experience with real hardware resources for understanding how they work.

One way to get acquainted with the development of hardware is the use of so-called field programmable gate arrays FPGA, which are reconfigurable device type [1].

In this work presents one of the main stages of creating a virtual FPGA laboratory – developing a method of emulation peripherals.

1. Topic currency

Nowadays, there are many directions for students who choose to study the area of computer science and technologies. Choosing a single direction for further study is influenced by many factors. For programmers, who study languages like C, C++, C#, Java and so on, it is enough to have one of the open source compilers and notepad. For programmers, who study hardware components of computer systems, for example, FPGA, it is necessary to have software packages and various kinds of chips and boards for experiments. Creating a virtual FPGA laboratory will help to make experiments on real hardware, which will help teaching of specialists in the field of computer engineering.

Masterwork is devoted to development of a method for emulating virtual peripherals for virtual FPGA-lab. The target FPGA boards are Xilinx boards [2]. These boards have high functionality, which allows to use them for the implementation of real devices and to test different kinds of hardware devices, and for prototyping. CAD Xilinx ISE, Xilinx ChipScope Pro, Aldec Active-HDL, Hardware Debugger were used in this masterwork.

2. Aim and tasks of research

The aim of research is development of software and hardware method of working with remote FPGA-board and interact with peripheral devices or their models, for example, by ports like PS/2, Uart etc.

The main tasks of research:

  1. Study of architecture of Xilinx FPGA boards
  2. Analysis of platforms with remote access to FPGA-resources
  3. Analysis of existing methods of emulation of peripherals on FPGA boards.
  4. Study communication interface of peripheral ports.
  5. Development of software and hardware emulation method of peripherals on FPGA board.

The object of researchis FPGA-projects such as system-on-chip.

The subject of researchis the peripheral ports and interfaces of information interaction.

Scientific novelty: there was developed peripheral devices emulation method for microprocessor architecture of FPGA. It based on microprocessor Microblaze. This method has sufficiently universal character, because it allows to imitate the most part of peripheral devices.

Results, which were obtained in this masterwork, will be used to create a virtual FPGA laboratory.

3. Overview of research and same projects

Currently in the world there are several projects developed FPGA virtual laboratory. They implemented the ability to work with digital sensors (buttons, switches, etc) on most FPGA board with some peripheral ports, for example, PS/2.

To do this, different methods are used. One method involves the use of a further input/output device which receives the user data via a special connector and sends signals FPGA board [3].

Another option - the creation of a program block that will emulate the periphery of FPGA board [4,5].

4. Study microprocessor architecture of Xilinx FPGA boards

4.1. Microblaze

Xilinx FPGA boards have Microblaze processor [6].

MicroBlaze is embedded soft-core processor with RISC-architecture that is optimized for the creation of systems-on-chip on Xilinx FPGA.

MicroBlaze has a universal means of communication with the periphery, providing the possibility of its widespread use in embedded system. Basic I/O bus - CoreConnect PLB Bus which can operate in master mode and slave. Most units are connected directly to the PLB. To access the internal memory of an FPGA (BRAM), MicroBlaze uses special bus LMB, which reduces the load on the other bus.

MicroBlaze microprocessor core structure is built on the principle of a Harvard architecture, which is based on the concept of using separate data bus and commands. Organization microprocessor highways according to this concept achieves high speed operations. Generalized structure of microprocessor core MicroBlaze is shown in Fig.1

Figure 1 - Architecture processor core MicroBlaze [7]

4.2. PLB Bus

The main interest in this structure represents PLB - Processor Local Bus. This 128-bit bus for connecting an arbitrary number of peripheral devices, working in master and slave. It consists of a control module of bus timer, program modules, reading and writing data, block addressing and additional DCL (Device Control Register) slave interface for register access errors [8]. Figure 2 shows a diagram of connecting devices to the bus PLB, provided by the developer.

Figure 2 - Wiring devices on the bus PLB

Thus, all communication with the FPGA board peripherals provided by a bus PLB.

FPGA board work with peripheral devices by means of peripheral ports, which organize data exchange between devices (FPGA board and specific peripheral device ) using a special interface, for example, PS/2, uart, vga, etc.

The work of virtual FPGA lab is assumes that the user has a set of data obtained from the actual peripheral device or of its model, which he sends with the project on a Web resource, and then these data take part in modeling of whole user project. Therefore, we need all emulators of all peripheral ports on a server-side, organizing information exchange between the FPGA boards and real peripherals. Also ist is necessary to create a variety of additional modules, such as memory buffers.

5. Development of a method emulation PS/2 port

5.1. Interface PS/2

For creating of an emulator of information exchange interface it is necessary to learn each interface. Let's start with the PS/2 interface, which is typically used to connect the PC keyboard and mouse.

PS/2 is a bidirectional interface that organizes information exchange between two devices. Physical port PS/2 is shown in Figure 3.

Figure 3 - Physical port PS/2 [9]

Algorithm of emulator PS/2 port, which organizes information exchange with the keyboard, is:

  1. Server receives user line, which was inputted on the client side of the web resource of FPGA virtual laboratory.
  2. On the next step user string sends to buffer on FPGA board.
  3. Next step is to send each character of string to the simulator keyboard.
  4. Keyboard simulator connects to the PS/2 port on the FPGA board.
  5. Simulator makes input of user string character by character directly into the PS/2 port.

Functional diagram of working of FPGA board with virtual keyboard is shown in Figure 4.

Figure 4 – Functional circuit of FPGA board and virtual keyboard interection

5.2. Keyboard simulator

The keyboard simulator sends each user symbol in the 1-bit format, which is shown in Table 1.

Table 1 - Format of the data packet from the keyboard to the FPGA- board

Bits Value
1 Start bit. Always 0
2–9 Data Bits. LSB – first
10 Parity Bit
11 Stop bit. Is always 1

The frequency of stroke of PS/2 port is 10-16.7 kHz. Time of Clock transition from "1" to Data change must be more than 5 microseconds. Time of Data changes to Clock transition to "0" must be more than 5 ms and less than 25 ms. Timing diagram, which illustrates data transmission from the device to the host through the PS/2 interface and the temporal characteristics of the signals are shown in figure 5 [10].

Figure 5 – Timing diagram of data transmission through the PS/2 port and temporal characteristics of the signals.

Software simulator was created with VHDL language [11], as a software add-on of microblaze processor.

When you create a keyboard simulator it is necessary to know next rules:

  1. Each key has a unique scan-code
  2. Pressing the scan-code is sent to the port
  3. When the key is released, break-code 0xF0 is sent to port
  4. When key is pressed for long time, scan-code is sent every 100 msec

5.3. VHDL model. Sending data from keyboard

Data transmission from the keyboard through the port P/ 2 can be realized as follows:

			Signal_State_Fromation: Process (Reset, CLK)
			begin	
				 if (Reset ='1') then
					 signal_state <= Start;
				 elsif (CLK'Event and CLK = '1') then
					 case signal_state is
						 when Start   => signal_state <= d0;
						 when d0       => signal_state <= d1;
						 when d1       => signal_state <= d2;
						 when d2       => signal_state <= d3;
						 when d3       => signal_state <= d4;
						 when d4       => signal_state <= d5; 
						 when d5       => signal_state <= d6;
						 when d6       => signal_state <= d7;	
						 when d7       => signal_state <= Parity;
						 when Parity => signal_state <= Stop;
						 when Stop   => signal_state <= Start;
						 when Others =>
					 End Case;	  
				end if;
			end process;

The timing diagram of data transmission through a PS/2 port is shown in Figure 6.

Figure 6 – Data transfer via the PS/2 port

5.4. VHDL model. Receiving data from a keyboard

Receiving data from the keyboard via PS/2 port can be realized as follows:

			case state_reg is
				when idle =>
					if fall_edge = '1' and rx_en = '1' then
					-- Shift in start bit
						b_next <= ps2d & b_reg(10 downto 1);
						n_next <= "1001";
						state_next <= dps;
					end if;
				when dps =>
				-- 8 data bits + 1 parity + 1 stop
					if fall_edge = '1' then
						b_next <= ps2d & b_reg (10 downto 1);
						if n_reg = 0 then
							state_next <= load;
						else
							n_next <= n_reg - 1;
						end if;
					end if;
				when load =>
					-- 1 extra clock to complete last shift
					state_next <= idle;
					rx_done_tick <= '1';
			end case;

The timing diagram of data receiving through the PS/2 port is shown in Figure 7.

Figure 7 Receiving data via PS/2 port

Now it is necessary to create a software module that will send an interrupt signal to processor microblaze of FPGA board when you press a key. It is necessary to give control to the appropriate simulator, which should send the information, which was entered by the user, directly to the PS/2 port. After that, the information, which was entered, should be processed by the user program.

Example of remote access to peripheral ports of FPGA board (Animation: – physical size 148KByte, frames count – 5, size – 1000õ233)
Figure 8 – Example of remote access to peripheral ports of FPGA board (Animation: – physical size 148KByte, frames count – 5, size – 1000õ233)

Next, you need to consider the organization of the microprocessor interrupt microblaze. First, you need to raise a bit, allowing the processor interrupt. If this is done, when a signal interrupts the microprocessor, it stops the execution of the current code and jumps to the address 0h00000010. Next, complete the following tasks:

  1. The current context is saved.
  2. Confirms acceptance of an interrupt signal.
  3. Realize interrupt.
  4. Restores the saved context and will return from interrupt.

In cases where there are multiple devices that can create an interrupt signal, the interrupt controller must be used, since there is only one microblaze interrupt input. When the interrupt routine, it asks the controller which device caused the interrupt and executes the corresponding interrupt [12].

Conclusions

At the time of creating of this page on the masters portal DonNTU this master's work is not complete. At this stage of the master's work can be identified that it was selected direction vector of the project and the main methods of implementation. The future plans are to implement software modules of simulators peripheral ports, which were created, as superstructure of microblaze FPGA processor boards and testing of their work. In future interfaces of information exchange will study deeper.

References

  1. Wikipedia: Field-programmable gate array Internet resource. Access mode: http://en.wikipedia.org/wiki/Field-programmable_gate_array
  2. Official website Xilinx, FPGA manufacturer schemes. Internet resource. Access mode: http://www.xilinx.com/
  3. A New Virtual Hardware Laboratory for Remote FPGA Experiments on Real Hardware. Access mode: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.217.8484&rep=rep1&type=pdf
  4. A Remote FPGA Laboratory for Digital Design Students. Access mode: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.378.7226
  5. REMOTE FIELD-PROGRAMMABLE GATE ARRAY (FPGA) LAB Access mode: http://ijret.org/Volumes/V03/I04/IJRET_110304149.pdf
  6. Rod Jesman, Fernando Martinez Vallina, Jafar Saniie Microblaze Turtorial p.36
  7. Microblaze processor reference guide. Internet resource. Access mode: : http://www.xilinx.com/support/documentation/sw_manuals/mb_ref_guide.pdf
  8. LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a) Èíòåðíåò ðåñóðñ. –– Ðåæèì äîñòóïà: http://www.xilinx.com/support/documentation/ip_documentation/plb_v46.pdf
  9. Protocol PS/2, work with mouse and keyboard. Internet resource. Mode of access: http://www.computer-engineering.org/ps2protocol/
  10. PS/2 port. Internet resource. Mode of access: http://en.wikipedia.org/wiki/PS/2_connector
  11. Peter J. Ashenden, Jim Lewis. The Designer's Guide to VHDL. - 3rd ed. - Burlington: Library of Congress Cataloging-in-Publication Data, 2008.
  12. Microblaze interrupt system. Internet resource. Access mode: http://www1.cs.columbia.edu/~soviani/cs4840hack/Microblaze_interrupts.html