Computer Science and Technology
Computer engineering
Computing Machines, Complexes, Systems and Networks
Informatics and Computer Engineering, specializing
Computing Machines, Complexes, Systems and Networks, baccalaureate
Informatics and Computer Engineering, specializing
Computing Machines, Complexes, Systems and Networks, magistracy
When writing this essay master's work is not yet completed. Final Completion: June 2019. Full text of the work and materials on the topic can be obtained from the author or from his scientific adviser after the specified date.
Every year, the role of computer equipment increases, while all components of computer systems are located on integrated circuits, not allowing access to individual nodes or elements, thereby complicating the process of studying the functioning of computer systems and their components.
A deep understanding of the principles of construction and operation of complex systems is achieved only through practical work with such systems or their models. Even the most detailed description of working with a basic digital device and detailed illustrations of the process of executing commands cannot replace actual work with this device.
This problem is particularly relevant in technical universities, and special models are being developed for its solution: physical or functional [1], which clearly demonstrate data presentation, operations, interaction with peripherals by means of input-output operations and interrupt system.
To support the disciplines of the hardware direction, we need models that allow us to consider pipelining of commands, speculative execution, data caching, as well as various architectures of processor elements, such as: superscalar architecture, VLIW, vector processors. Also, you should additionally consider the process of compiling and optimizing machine code for various architectures.
The modern world is already difficult to imagine without computing, and its main components are still processor elements. For technical universities, it is especially important to prepare students with an understanding of the principles of operation of processors, the principles of their functioning and the diversity of architectures. The demonstration models that clearly demonstrate the operation of a component of a device in a certain situation, i.e. educational material can be presented more effectively.
A multi-level demonstration model of a hypothetical computer will allow you to visually demonstrate the operation of processor components, their interaction with memory, and other peripheral devices.
This master's work is devoted to the development of a functional demonstration model, as well as the development of a compiler for this model and the study of ways to optimize the generation of machine code.
As a result of the work, it is planned to consider various processor architectures, general processor technologies, such as pipeline processing team, speculative execution, conversion prediction, data caching. Develop a functional demo model, and an optimizing compiler for it.
A superscalar processor[10] is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor that can execute at most one single instruction per clock cycle, a superscalar processor can execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution units on the processor. It therefore allows for more throughput (the number of instructions that can be executed in a unit of time) than would otherwise be possible at a given clock rate. Each execution unit is not a separate processor (or a core if the processor is a multi-core processor), but an execution resource within a single CPU such as an arithmetic logic unit.
VLIW architectures[9] (Very Long Instruction Word) are distinct from traditional RISC and CISC architectures implemented in current mass-market microprocessors. It is important to distinguish instruction-set architecture – the processor programming model–from implementation–the physical chip and its characteristics. VLIW microprocessors and superscalar implementations of traditional instruction sets share some characteristics–multiple execution units and the ability to execute multiple operations simultaneously. The techniques used to achieve high performance, however, are very different because the parallelism is explicit in VLIW instructions but must be discovered by hardware at run time by superscalar processors. VLIW implementations are simpler for very high performance. Just as RISC architectures permit simpler, cheaper high-performance implementations than do CISCs, VLIW architectures are simpler and cheaper than RISCs because of further hardware simplifications. VLIW architectures, however, require more compiler support.
Speculative execution is an optimization technique where a computer system performs some task that may not be needed. Work is done before it is known whether it is actually needed, so as to prevent a delay that would have to be incurred by doing the work after it is known that it is needed. If it turns out the work was not needed after all, most changes made by the work are reverted and the results are ignored.
The role of computing is increasing every year. Computers are becoming increasingly difficult, respectively, and the level of training of specialists in technical universities should grow. And to achieve the required level of preparation of students of instrumental disciplines, in the course of this work a multilevel model of a hypothetical computer will be developed that clearly demonstrate data presentation, operations, interaction with peripherals using input-output operations and an interrupt system.
The multi-level model will allow to consider pipelined processing of commands, speculative execution, data caching, as well as various architectures of processor elements, such as: superscalar architecture, VLIW, vector processors. There will also be considered the process of compiling and optimizing machine code for various architectures.