Abstract of master's work

Author: Svyezhentsev Yuriy
Lider: Doctor of technical science Bashkov Y.A.
Master’s work subject: «Research and development of effective methods of construction of generation of a code for expressions of language Verilog»

Table of contents

Introduction and urgency

Scientific novelty

Introduction in language of the description of equipment Verilog

Expressions in language Verilog

Table 1-Operators in Verilog HDL

Compiler's organization

Introduction and urgency

Presently it is impossible to present a life without various technics. The mankind has so got used to automation, to such mass media and entertainments as the TV, radio, a computer, etc, that it is impossible to exist without similar things. All this - the electrical engineer. Practically at any even a household subject there are elements of electronics. Even modern washing machines have electronic management. Thus, very actual problem and a problem is development and creation of a various sort of electric schemes. For development there is a set of computer systems which have the visual interface and allow easily enough, quickly, it is convenient and to model this or that idea with a lot of opportunities. But process of creation of a microcircuit frequently is complex and expensive. Therefore is inexpedient to make a detail if we were not convinced of its utility, working capacity, etc. The good decision of this problem was creation of simulators which allow without creation of a microcircuit, программно промоделировать its behaviour, to test it, etc. the Equipment is described on HDL (Hardware Description Language) - language of the description of the equipment. One of the primary goals of a simulator is compilation of a HDL-code in a machine code. Compilation - one of the oldest and challenges in programming. The theme of my master's work is a research and development of a part of the compiler of language Verilog. Compilation consists of several stages. One of stages is generation of an intermediate code from treelike representation of a code of language Verilog. One of subtasks of this stage is generation of a code for expression of language Verilog. This problem is one challenges of compilation of language Verilog. Complexity consists that languages of the description of the equipment have set of non-standard types of the given and various operations which cannot be met in one other programming language. Therefore, transformation of expressions of language of the description of the equipment to the intermediate code which is easily giving in for generation of a machine code, is the complex and volumetric problem having set of problems and subtasks. thus, the problem of generation of a code for today is very actual and complex.

Scientific novelty

In the world there are four firms which are engaged in development of simulators of work of electric schemes. In a problem of compilation of a HDL-code are engaged for a long time and the set of algorithms is created. But, as, the hardware device can be very much greater and carrying out very much challenges (for example, processors) process of compilation and simulation can borrow a lot of time - days, weeks, etc., and also to demand a plenty of resources. Therefore, the primary goals are: - optimum generation of a code - creation of such algorithms which at compilation demanded a minimum of time and a minimum of system resources; - generation of an optimum code - creation of such algorithms which generated an optimum code which during simulation had minimal time of simulation and the minimum of system resources demanded; - creation of the generator easily expanded for support of new expressions of language Verilog, and also expressions of other languages of the description of the equipment; - creation of the generator, capable to work with expressions very much great volume. Each of these problems is complex. Scientific novelty consists in creation of any idea or any algorithm, more optimum, than existing.

Introduction in language of the description of equipment Verilog

The Verilog hardware description language (HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice by an overwhelming number of integrated circuit (IC) designers. Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches, and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels is essentially provided by the semantics of two data types: nets and variables. Continuous assignments, in which expressions of both variables and nets can continuously drive values onto nets, provide the basic structural construct. Procedural assignments, in which the results of calculations involving variable and net values can be stored into variables, provide the basic behavioral construct. A design consists of a set of modules, each of which has an input/output (I/O) interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets. The Verilog language is extensible via the programming language interface (PLI) and the Verilog procedural interface (VPI) routines. The PLI/VPI is a collection of routines that allows foreign functions to access information contained in a Verilog HDL description of the design and facilitates dynamic interaction with simulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulation and computer-assisted design (CAD) systems, customized debugging tasks, delay calculators, and annotators. The language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of Defense. HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verification simulation, timing analysis, fault simulation, and test generation. In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent Open Verilog International (OVI) was formed to manage and promote Verilog HDL. In 1992, the Board of Directors of OVI began an effort to establish Verilog HDL as an IEEE standard. In 1993, the first IEEE working group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard as IEEE Std 1364-1995. After the standardization process was complete, the IEEE P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. This led to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001. With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identify outstanding issues with the language as well as ideas for possible enhancements. As Accellera began working on standardizing SystemVerilog in 2001, additional issues were identified that could possibly have led to incompatibilities between Verilog 1364 and SystemVerilog. The IEEE P1364 Working Group was established as a subcomittee of the SystemVerilog P1800 Working Group to help ensure consistent resolution of such issues. The result of this collaborative work is this standard, IEEE Std 1364-2005.

Expressions in language Verilog

This clause describes the operators and operands available in the Verilog HDL and how to use them to form expressions. An expression is a construct that combines operands with operators to produce a result that is a function of the values of the operands and the semantic meaning of the operator. Any legal operand, such as a net bitselect, without any operator is considered an expression. Wherever a value is needed in a Verilog HDL statement, an expression can be used. Some statement constructs require an expression to be a constant expression. The operands of a constant expression consist of constant numbers, strings, parameters, constant bit-selects and part-selects of parameters, constant function calls, and constant system function calls only; but they can use any of the operators defined in Table 1. Constant system function calls are calls to certain built-in system functions where the arguments are constant expressions. When used in constant expressions, these function calls shall be evaluated at elaboration time. The system functions that may be used in constant system function calls are pure functions, i.e., those whose value depends only on their input arguments and which have no side effects. The data types reg, integer, time, real, and realtime are all variable data types. Descriptions pertaining to variable usage apply to all of these data types. An operand can be one of the following: - Constant number (including real) or string - Parameter (including local and specify parameters) - Parameter (not real) bit-select or part-select (including local and specify parameters) - Net - Net bit-select or part-select - reg, integer, or time variable - reg, integer, or time variable bit-select or part-select - real or realtime variable - Array element - Array element (not real) bit-select or part-select - A call to a user-defined function or system-defined function that returns any of the above The symbols for the Verilog HDL operators are similar to those in the C programming language. Table 1 lists these operators.

Table 1-Operators in Verilog HDL

{} {{}}	Concatenation, replication
unary + unary -	Unary operators
+ - * / **	Arithmetic
%	Modulus
> >= < <=	Relational
!	Logical negation
&&	Logical and
||	Logical or
==	Logical equality
!=	Logical inequality
===	Case equality
!==	Case inequality
~	Bitwise negation
&	Bitwise and
|	Bitwise inclusive or
^	Bitwise exclusive or
^~ or ~^	Bitwise equivalence
&	Reduction and
~&	Reduction nand
|	Reduction or
~|	Reduction nor
^	Reduction xor
~^ or ^~	Reduction xnor
<<	Logical left shift
>>	Logical right shift
<<<	Arithmetic left shift
>>>	Arithmetic right shift
? :	Conditional

Compiler's organization

Compilation theory - one of oldest theories of programming. There are many different theories. One of them propose existence and order of components, that have presented by animation: