Источник: Інформаційні керуючі системи та комп'ютерний моніторинг - 2010 / Матеріали I науково-технічної конференції молодих учених та студентів. — Донецьк, ДонНТУ — 2010, с. 151-154.

 
FEATURES OF PROCESSOR DESIGN USING RISC AND CISC ARCHITECTURE

 

Молодых А.Г. Новиков О.И.

Донецкий национальный технически университет г. Донецк

Кафедра компьютерной инженерии

E-mail:  Kovalev@donntu.ru

In the following article some features of processor design using CISC and RISC architecture are shown, discussed particularities of RISC and CISC architecture.

1.      CISC architecture particularities

The CISC machine is not the result of a particular philosophy of machine design. Rather, it resulted from the efforts of designers to incorporate more features such as addressing modes and instruction types in an environment were memory costs and access times were high, and a premium was placed on compact instruction codes.

When the MC6800 was introduced, 16 К RAM chips cost $500, and 40 MB hard disk drives cost $55,000. When the MC68000 was introduced, 64 К RAM chips still cost several hundred dollars, and 10 MB hard drives cost $5,000. Program and data storage were at a premium.

As succeeding generations of computers were developed, manufacturers continued to offer upward compatibility from simpler models to faster and more capable models, and it was only natural that the added capability would involve more complexity. Upward compatibility virtually demanded the introduction of complexity.

Furthermore, machine architects were aware of the "semantic gap," that is, the gap that existed between machine instruction sets and high-level language constructs. It was felt that narrowing the gap with complicated instructions and addressing modes would lead to performance increases. The compiler writers rejected most of these "improvements," finding that they did not fit well with language requirements or that they were of only limited usefulness. Research conducted in 1971 by Donald Knuth and in 1982 by David Patterson showed that 85% of a program's statements were assignment, conditional, or procedure calls. Nearly 80% of the assignment statements were MOVE instructions, without arithmetic operations. As the manufacturers added capabilities to their processors, they found that it was increasingly difficult to support higher clock speeds that would have otherwise been possible. Complex instructions and addressing modes worked against faster clock speeds, because of the greater number of microscopic actions that had to be performed per instruction.

Until recently RAM memory had been dropping in price approximately 40% per year. At a certain point, RAM prices had dropped sufficiently so that the pressure on system designers was less to design instructions that "did more" than it was to design systems that were faster. It was also becoming cost-effective to employ small amounts of higher-speed cache memory to reduce memory latency latency—the waiting time between when a memory request is made and when it has been satisfied.

            Operand Access Paths-Addressing Modes of the MC68000 Access paths to memory and register operands (addressing modes) are usually specified by a 6-bit field within the instruction as shown in Table. The figure at the top of the table shows the 6-bit effective address (EA) specifier. The meanings of mode and register fields are described in the table footnotes.

-When the 6-bit field specifies the destination operand of a MOVE instruction, the mode and reg   fields are reversed.

-An and Dn denote one of the eight address or data registers respectively.

-WS = word size in bytes: 1, 2, or 4.

-disp8 and disp16 are 8- and 16-bit displacements.

-Xn is one of D0-D7, or A0-A7.

-XnLo is the low-order 16 bits of register Xn, sign-extended to 32 bits.

-All values smaller than 32 bits are sign-extended to 32 bits before addition.

-Data is an 8-, 16- or 32-bit value as indicated by .B, .W, or .L in the instruction.

 

2.      RISC architecture

RISC - reduced instruction set computer, focuses on reducing the number and complexity of instructions in the machine. Actually, there are a number of strategies that are employed by RISC designers to exploit caching, pipelining, superscalarity, and so on.

One Instruction per Cycle This seemingly simple concept is possibly the most important in RISC design. With the common use of pipelining, the current goal is that (at least) one instruction will issue per clock cycle. Since program execution time depends on throughput, and not on individual instruction execution times, issuing instructions at an average rate of one per cycle is the correct goal. The key is to do this by making instructions simple, not by making clock periods longer.

Fixed Instruction Length If one instruction is to issue per clock cycle, it is natural that RISC designers would limit all instructions to a fixed length, usually 1 word. That word specifies everything there is to know about the instruction: what the operation is; where to get the operands, if there are operands; where to put the result, if there is a result; and where to find the next instruction.

Only Load and Store Instructions Access Memory This clean partitioning of processor activities between operand access and operations minimizes traffic between the processor and memory, and assures that all operands will be in registers when they are needed. This in turn minimizes pipeline delays due to absence of an operand.

Simplified Addressing Modes Complicated addressing modes mean longer clock periods, since there is more address arithmetic to perform. RISC machines usually limit themselves to only two addressing modes: register indirect and indexed, where the index may be in a register or may be an immediate constant that is contained within the instruction.

Fewer, Simpler Operations Simpler operations imply shorter clock cycles, since less has to be done in a given clock cycle. There is no room in the RISC instruction set for perhaps the most characteristic CISC VAX instruction, POLY, which evaluates a polynomial by Horner's method. Any given complex instruction can be decomposed into a sequence of simpler instructions. If the cache is able to keep up with the execution of these instructions, then the only penalty is increased use of RAM storage.

Delayed Loads and Branches In certain RISC architectures, loads, stores, and branch instructions require more than a single clock cycle to execute. In the case of loads and stores, this delay occurs because of time required to access memory, and in the latter case it occurs because of the delay in accessing the instruction stored at the branch address.

Prefetch and Speculative Execution Because all instructions are one word long, it becomes more feasible to examine instructions as they enter the pipeline to see if they involve operand access or branching. If they do, the operand or branch target can be prefetched, resulting effectively in zero execution time for the branch instruction or operand access. Having the branch target address available, and having several functional units that can execute multiple instructions in parallel, some processors begin execution at the target address in advance of knowing whether the condition has been met, and discard the results if it has not. This is speculative known as speculative execution.

Summary

Machine price and performance are the driving forces in the growth of the computer industry. Machine performance can me measured in many ways, from simple wall clock measurements or MIPS rates to more sophisticated measures that attempt to mimic real-world performance, such as Whetstone or Dhrystone counts. More recently the SPEC benchmarks have used real-world programs in suites that allow a more focused and realistic approach to performance measurement.

            CISC machines are characterized by instructions and addressing modes that emphasize economy of encoding. The result is instructions that vary widely in word length, number of memory accesses, and instruction execution time, and addressing modes that encourage memory traffic. These ISAs were appreciated at a time of higher memory costs. However, when CISC designers tried to apply hardware techniques to speed up execution, such as pipelined operation and superscalar designs, they found that complicated instructions and addressing modes interfered.

            RISC machines place much emphasis on single-word instructions and a load/store type of memory access. Architects find that simpler instructions with fixed word size and limited-memory operand access fit better with architectural speedup methods such as pipelining and superscalar operation. Simpler instructions and addressing modes also allow faster clock frequencies. Simpler instructions do require more memory and more memory access, but faster memory and instruction prefetch techniques have eliminated or greatly reduced the penalty, and more than compensated for by simpler CPU design, faster clock frequencies, and pipelining and superscalar operation.

           

References

J. Wakerly, Microcomputer Architecture and Programming: The 68000 Family, John Wiley & Sons, New York, 1989.

R.P. Colowell, C.Y. Hitchcock III, E.D. Jensen, H.M.B. Sprunt, and C.P. Kollar, “Computers complexity and controversy” IEEE Computer Magazine, vol. 18 (sept. 1985), pp. 8-19.