VHDL contains a number of facilities for modifying the state of objects and controlling the flow of execution of models. These are discussed in this section.
As in other programming languages, a variable is given a new value using an assignment statement. The syntax is:
variable_assignment_statement ::= target := expression ;
target ::= name | aggregate
In the simplest case, the target of the assignment is an object name, and the value of the expression is given to the named object. The object and the value must have the same base type.
If the target of the assignment is an aggregate, then the elements listed must be object names, and the value of the expression must be a composite value of the same type as the aggregate. Firstly, all the names in the aggregate are evaluated, then the expression is evaluated, and lastly the components of the expression value are assigned to the named variables. This is effectively a parallel assignment. For example, if a variable r is a record with two fields a and b, then they could be exchanged by writing
(a => r.b, b => r.a) := r
(Note that this is an example to illustrate how such an assignment works; it is not an example of good programming practice!)
The if statement allows selection of statements to execute depending on one or more conditions. The syntax is:
if_statement ::=
if condition then
sequence_of_statements
{ elsif condition then
sequence_of_statements
}
[ else
sequence_of_statements
]
end if ;
The conditions are expressions resulting in boolean values. The conditions are evaluated successively until one found that yields the value true. In that case the corresponding statement list is executed. Otherwise, if the else clause is present, its statement list is executed.
The case statement allows selection of statements to execute depending on the value of a selection expression. The syntax is:
case_statement ::=
case expression is
case_statement_alternative
{
case_statement_alternative }
end case ;
case_statement_alternative ::=
when choices =>
sequence_of_statements
choices ::= choice { | choice }
choice ::=
simple_expression
| discrete_range
| element_simple_name
| others
The selection expression must result in either a discrete type, or a one-dimensional array of characters. The alternative whose choice list includes the value of the expression is selected and the statement list executed. Note that all the choices must be distinct, that is, no value may be duplicated. Furthermore, all values must be represented in the choice lists, or the special choice others must be included as the last alternative. If no choice list includes the value of the expression, the others alternative is selected. If the expression results in an array, then the choices may be strings or bit strings.
Some examples of case statements:
case element_colour of
when red =>
statements
for red;
when green | blue =>
statements
for green or blue;
when orange to turquoise
=>
statements
for these colours;
end case;
case opcode of
when X"00" => perform_add;
when X"01" => perform_subtract;
when others => signal_illegal_opcode;
end case;
VHDL has a basic loop statement, which can be augmented to form the usual while and for loops seen in other programming languages. The syntax of the loop statement is:
loop_statement ::=
[ loop_label : ]
[
iteration_scheme ] loop
sequence_of_statements
end
loop [ loop_label ] ;
iteration_scheme ::=
while condition
| for loop_parameter_specification
parameter_specification ::=
identifier in discrete_range
If the iteration scheme is omitted, we get a loop which will repeat the enclosed statements indefinitely. An example of such a basic loop is:
loop
do_something;
end loop;
The while iteration scheme allows a test condition to be evaluated before each iteration. The iteration only proceeds if the test evaluates to true. If the test is false, the loop statement terminates. An example:
while index < length and str(index) /= ' ' loop
index := index + 1;
end loop;
The for iteration scheme allows a specified number of iterations. The loop parameter specification declares an object which takes on successive values from the given range for each iteration of the loop. Within the statements enclosed in the loop, the object is treated as a constant, and so may not be assigned to. The object does not exist beyond execution of the loop statement. An example:
for item in 1 to last_item loop
table(item) := 0;
end loop;
There are two additional statements which can be used inside a loop to modify the basic pattern of iteration. The 'next' statement terminates execution of the current iteration and starts the subsequent iteration. The 'exit' statement terminates execution of the current iteration and terminates the loop. The syntax of these statements is:
next_statement ::= next [ loop_label ] [ when condition ] ;
exit_statement ::= exit [ loop_label ] [ when condition ] ;
If the loop label is omitted, the statement applies to the inner-most enclosing loop, otherwise it applies to the named loop. If the when clause is present but the condition is false, the iteration continues normally. Some examples:
for i in 1 to max_str_len loop
a(i) := buf(i);
exit when buf(i) = NUL;
end loop;
outer_loop : loop
inner_loop : loop
do_something;
next
outer_loop when temp = 0;
do_something_else;
end loop inner_loop;
end loop outer_loop;
The null statement has no effect. It may be used to explicitly show that no action is required in certain cases. It is most often used in case statements, where all possible values of the selection expression must be listed as choices, but for some choices no action is required. For example:
case controller_command is
when forward => engage_motor_forward;
when reverse => engage_motor_reverse;
when idle => null;
end case;
An assertion statement is used to verify a specified condition and to report if the condition is violated. The syntax is:
assertion_statement ::=
assert condition
[
report expression ]
[
severity expression ] ;
If the report clause is present, the result of the expression must be a string. This is a message which will be reported if the condition is false. If it is omitted, the default message is "Assertion violation". If the severity clause is present the expression must be of the type severity_level. If it is omitted, the default is error. A simulator may terminate execution if an assertion violation occurs and the severity value is greater than some implementation dependent threshold. Usually the threshold will be under user control.