cookbook

Contents

1. Introduction

1.1. Describing Structure

1.2. Describing Behaviour

1.3. Discrete Event Time Model

1.4. A Quick Example

2. VHDL is Like a Programming Language

2.1. Lexical Elements

2.1.1. Comments

2.1.2. Identifiers

2.1.4. Characters

2.1.6. Bit Strings

2.2. Data Types and Objects

2.2.1. Integer Types

2.2.2. Physical Types

2.2.3. Floating Point Types

2.2.4. Enumeration Types

2.2.7. Subtypes

2.2.8. Object Declarations

2.2.9. Attributes

2.3. Expressions and Operators

2.4. Sequential Statements

2.4.1. Variable Assignment

2.4.2. If Statement

2.4.3. Case Statement

2.4.4. Loop Statements

2.4.5. Null Statement

2.4.6. Assertions

2.5. Subprograms and Packages

2.5.1. Procedures and Functions

2.5.2. Overloading

2.5.3. Package and Package Body Declarations

2.5.4. Package Use and Name Visibility

3. VHDL Describes Structure

3.1. Entity Declarations

3.2. Architecture Declarations

3.2.1. Signal Declarations

3.2.3. Component Declarations

3.2.4. Component Instantiation

4. VHDL Describes Behaviour

4.1. Signal Assignment

4.2. Processes and the Wait Statement

4.3. Concurrent Signal Assignment Statements

4.3.1. Conditional Signal Assignment

4.3.2. Selected Signal Assignment

5. Model Organisation

5.1. Design Units and Libraries

5.2. Configurations

5.3. Complete Design Example

6. Advanced VHDL

6.1. Signal Resolution and Buses

6.2. Null Transactions

6.3. Generate Statements

6.4. Concurrent Assertions and Procedure Calls

6.5. Entity Statements

7. Sample Models: The DP32 Processor

7.1. Instruction Set Architecture

7.2. Bus Architecture

7.3. Types and Entity

7.4. Behavioural Description

7.5. Test Bench

7.6. Register Transfer Architecture

7.6.1. Multiplexor

7.6.2. Transparent Latch

7.6.3. Buffer

7.6.4. Sign Extending Buffer

7.6.5. Latching Buffer

7.6.6. Program Counter Register

7.6.7. Register File

7.6.8. Arithmetic & Logic Unit

7.6.9. Condition Code Comparator

7.6.10. Structural Architecture of the DP32