VHDL provides a number of basic, or scalar, types, and a means of forming composite types. The scalar types include numbers, physical quantities, and enumerations (including enumerations of characters), and there are a number of standard predefined basic types. The composite types provided are arrays and records. VHDL also provides access types (pointers) and files, although these will not be fully described in this booklet.
A data type can be defined by a type declaration:
full_type_declaration ::= type identifier is type_definition ;
type_definition :=
scalar_type_definition
| composite_type_definition
| access_type_definition
| file_type_definition
scalar_type_definition ::=
enumeration_type_definition | integer_type_definition
| floating_type_definition | physical_type_definition
composite_type_definition ::=
array_type_definition
| record_type_definition
Examples of different kinds of type declarations are given in the following sections.
An integer type is a range of integer values within a specified range. The syntax for specifying integer types is:
integer_type_definition ::= range_constraint
range_constraint ::= range range
range ::= simple_expression direction simple_expression
direction ::= to | downto
The expressions that specify the range must of course evaluate to integer numbers. Types declared with the keyword to are called ascending ranges, and those declared with the keyword downto are called descending ranges. The VHDL standard allows an implementation to restrict the range, but requires that it must at least allow the range -2147483647 to +2147483647.
Some examples of integer type declarations:
type byte_int is range 0 to 255;
type signed_word_int is range -32768 to 32767;
type bit_index is range 31 downto 0;
There is a predefined integer type called integer. The range of this type is implementation defined, though it is guaranteed to include -2147483647 to +2147483647.
A physical type is a numeric type for representing some physical quantity, such as mass, length, time or voltage. The declaration of a physical type includes the specification of a base unit, and possibly a number of secondary units, being multiples of the base unit. The syntax for declaring physical types is:
physical_type_definition ::=
range_constraint
units
base_unit_declaration
{
secondary_unit_declaration }
end
units
base_unit_declaration ::= identifier ;
secondary_unit_declaration ::= identifier = physical_literal ;
physical_literal ::= [ abstract_literal ] unit_name
Some examples of physical type declarations:
type length is range 0 to 1E9
units
um;
mm = 1000
um;
cm = 10
mm;
m = 1000
mm;
in = 25.4
mm;
ft = 12
in;
yd = 3
ft;
rod = 198
in;
chain =
22 yd;
furlong
= 10 chain;
end units;
type resistance is range 0 to 1E8
units
ohms;
kohms =
1000 ohms;
Mohms =
1E6 ohms;
end units;
The predefined physical type time is important in VHDL, as it is used extensively to specify delays in simulations. Its definition is:
type time is range implementation_defined
units
fs;
ps = 1000
fs;
ns = 1000
ps;
us = 1000
ns;
ms = 1000
us;
sec = 1000
ms;
min = 60
sec;
hr = 60
min;
end units;
To write a value of some physical type, you write the number followed by the unit. For example:
10 mm 1 rod 1200 ohm 23 ns
A floating point type is a discrete approximation to the set of real numbers in a specified range. The precision of the approximation is not defined by the VHDL language standard, but must be at least six decimal digits. The range must include at least -1E38 to +1E38. A floating point type is declared using the syntax:
floating_type_definition := range_constraint
Some examples are:
type signal_level is range -10.00 to +10.00;
type probability is range 0.0 to 1.0;
There is a predefined floating point type called real. The range of this type is implementation defined, though it is guaranteed to includ -1E38 to +1E38.
An enumeration type is an ordered set of identifiers or characters. The identifiers and characters within a single enumeration type must be distinct, however they may be reused in several different enumeration types.
The syntax for declaring an enumeration type is:
enumeration_type_definition ::= ( enumeration_literal { , enumeration_literal } )
enumeration_literal ::= identifier | character_literal
Some examples are:
type logic_level is (unknown, low, undriven, high);
type alu_function is (disable, pass, add, subtract, multiply, divide);
type octal_digit is ('0', '1', '2', '3', '4', '5', '6', '7');
There are a number of predefined enumeration types, defined as follows:
type severity_level is (note, warning, error, failure);
type boolean is (false, true);
type bit is ('0', '1');
type character is (
NUL, SOH, STX, ETX, EOT,
ENQ, ACK, BEL,
BS, HT, LF, VT,
FF, CR, SO, SI,
DLE, DC1, DC2, DC3, DC4,
NAK, SYN, ETB,
CAN, EM, SUB, ESC, FSP,
GSP, RSP, USP,
' ', '!', '"', '#', '$',
'%', '&', ''',
'(', ')', '*', '+', ',',
'-', '.', '/',
'0', '1', '2', '3', '4',
'5', '6', '7',
'8', '9', ':', ';', '<',
'=', '>', '?',
'@', 'A', 'B', 'C', 'D',
'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L',
'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T',
'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\',
']', '^', '_',
'`', 'a', 'b', 'c', 'd',
'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l',
'm', 'n', 'o',
'p', 'q', 'r', 's', 't',
'u', 'v', 'w',
'x', 'y', 'z', '{', '|',
'}', '~', DEL);
Note that type character is an example of an enumeration type containing a mixture of identifiers and characters. Also, the characters '0' and '1' are members of both bit and character . Where '0' or '1' occur in a program, the context will be used to determine which type is being used.
An array in VHDL is an indexed collection of elements all of the same type. Arrays may be one-dimensional (with one index) or multi-dimensional (with a number of indices). In addition, an array type may be constrained, in which the bounds for an index are established when the type is defined, or unconstrained, in which the bounds are established subsequently.
The syntax for declaring an array type is:
array_type_definition ::=
unconstrained_array_definition | constrained_array_definition
unconstrained_array_definition ::=
array ( index_subtype_definition
{ , index_subtype_definition } )
of
element_subtype_indication
constrained_array_definition ::=
array index_constraint of
element_subtype_indication
index_subtype_definition ::= type_mark range <>
index_constraint ::= ( discrete_range { , discrete_range } )
discrete_range ::= discrete_subtype_indication | range
Subtypes, referred to in this syntax specification, will be discussed in detail in Section 2.2.7.
Some examples of constrained array type declarations:
type word is array (31 downto 0) of bit;
type memory is array (address) of word;
type transform is array (1 to 4, 1 to 4) of real;
type register_bank is array (byte range 0 to 132) of integer;
An example of an unconstrained array type declaration:
type vector is array (integer range <>) of real;
The symbol '<>' (called a box) can be thought of as a place-holder for the index range, which will be filled in later when the array type is used. For example, an object might be declared to be a vector of 20 elements by giving its type as:
vector(1 to 20)
There are two predefined array types, both of which are unconstrained. They are defined as:
type string is array (positive range <>) of character;
type bit_vector is array (natural range <>) of bit;
The types positive and natural are subtypes of integer, defined in Section 2.2.7 below. The type bit_vector is particularly useful in modeling binary coded representations of values in simulations of digital systems.
An element of an array object can referred to by indexing the name of the object. For example, suppose a and b are one- and two-dimensional array objects respectively. Then the indexed names a(1) and b(1, 1) refer to elements of these arrays. Furthermore, a contiguous slice of a one-dimensional array can be referred to by using a range as an index. For example a(8 to 15) is an eight-element array which is part of the array a.
Sometimes you may need to write a literal value of an array type. This can be done using an array aggregate, which is a list of element values. Suppose we have an array type declared as:
type a is array (1 to 4) of character;
and we want to write a value of this type containing the elements 'f', 'o', 'o', 'd' in that order. We could write an aggregate with positional association as follows:
('f', 'o', 'o', 'd')
in which the elements are listed in the order of the index range, starting with the left bound of the range. Alternatively, we could write an aggregate with named association:
(1 => 'f', 3 => 'o', 4 => 'd', 2 => 'o')
In this case, the index for each element is explicitly given, so the elements can be in any order. Positional and named association can be mixed within an aggregate, provided all the positional associations come first. Also, the word others can be used in place of an index in a named association, indicating a value to be used for all elements not explicitly mentioned. For example, the same value as above could be written as:
('f', 4 => 'd', others => 'o')
VHDL provides basic facilities for records, which are collections of named elements of possibly different types. The syntax for declaring record types is:
record_type_definition ::=
record
element_declaration
{ element_declaration
}
end record
element_declaration ::= identifier_list : element_subtype_definition ;
identifier_list ::= identifier { , identifier )
element_subtype_definition ::= subtype_indication
An example record type declaration:
type instruction is
record
op_code
: processor_op;
address_mode
: mode;
operand1,
operand2: integer range 0 to 15;
end record;
When you need to refer to a field of a record object, you use a selected name. For example, suppose that r is a record object containing a field called f. Then the name r.f refers to that field.
As for arrays, aggregates can be used to write literal values for records. Both positional and named association can be used, and the same rules apply, with record field names being used in place of array index names.
The use of a subtype allows the values taken on by an object to be restricted or constrained subset of some base type. The syntax for declaring a subtype is:
subtype_declaration ::= subtype identifier is subtype_indication ;
subtype_indication ::= [ resolution_function_name ] type_mark [ constraint ]
type_mark ::= type_name | subtype_name
constraint ::= range_constraint | index_constraint
There are two cases of subtypes. Firstly a subtype may constrain values from a scalar type to be within a specified range (a range constraint). For example:
subtype pin_count is integer range 0 to 400;
subtype digits is character range '0' to '9';
Secondly, a subtype may constrain an otherwise unconstrained array type by specifying bounds for the indices. For example:
subtype id is string(1 to 20);
subtype word is bit_vector(31 downto 0);
There are two predefined numeric subtypes, defined as:
subtype natural is integer range 0 to highest_integer
subtype positive is integer range 1 to highest_integer
An object is a named item in a VHDL description which has a value of a specified type. There are three classes of objects: constants, variables and signals. Only the first two will be discusses in this section; signals will be covered in Section 3.2.1. Declaration and use of constants and variables is very much like their use in programming languages.
A constant is an object which is initialised to a specified value when it is created, and which may not be subsequently modified. The syntax of a constant declaration is:
constant_declaration ::=
constant identifier_list : subtype_indication
[ := expression ] ;
Constant declarations with the initialising expression missing are called deferred constants, and may only appear in package declarations (see Section 2.5.3). The initial value must be given in the corresponding package body. Some examples:
constant e : real := 2.71828;
constant delay : Time := 5 ns;
constant max_size : natural;
A variable is an object whose value may be changed after it is created. The syntax for declaring variables is:
variable_declaration ::=
variable identifier_list : subtype_indication [ := expression
] ;
The initial value expression, if present, is evaluated and assigned to the variable when it is created. If the expression is absent, a default value is assigned when the variable is created. The default value for scalar types is the leftmost value for the type, that is the first in the list of an enumeration type, the lowest in an ascending range, or the highest in a descending range. If the variable is a composite type, the default value is the composition of the default values for each element, based on the element types.
Some examples of variable declarations:
variable count : natural := 0;
variable trace : trace_array;
Assuming the type trace_array is an array of boolean, then the initial value of the variable trace is an array with all elements having the value false.
Given an existing object, it is possible to give an alternate name to the object or part of it. This is done using and alias declaration. The syntax is:
alias_declaration ::= alias identifier : subtype_indication is name ;
A reference to an alias is interpreted as a reference to the object or part corresponding to the alias. For example:
variable instr : bit_vector(31 downto 0);
alias op_code : bit_vector(7 downto 0) is instr(31 downto 24);
declares the name op_code to be an alias for the left-most eight bits of instr.
Types and objects declared in a VHDL description can have additional information, called attributes, associated with them. There are a number of standard pre-defined attributes, and some of those for types and arrays are discussed here. An attribute is referenced using the `'´ notation. For example,
thing'attr
refers to the attribute attr of the type or object thing.
Firstly, for any scalar type or subtype T, the following attributes can be used:
| Attribute | Result |
| T'left | Left bound of T |
| T'right | Right bound of T |
| T'low | Lower bound of T |
| T'high | Upper bound of T |
For an ascending range, T'left = T'low, and T'right = T'high. For a descending range, T'left = T'high, and T'right = T'low.
Secondly, for any discrete or physical type or subtype T, X a member of T, and N an integer, the following attributes can be used:
| Attribute | Result |
| T'pos(X) | Position number of X in T |
| T'val(N) | Value at position N in T |
| T'leftof(X) | Value in T which is one position left from X |
| T'rightof(X) | Value in T which is one position right from X |
| T'pred(X) | Value in T which is one position lower than X |
| T'succ(X) | Value in T which is one position higher than X |
For an ascending range, T'leftof(X) = T'pred(X), and T'rightof(X) = T'succ(X). For a descending range, T'leftof(X) = T'succ(X), and T'rightof(X) = T'pred(X).
Thirdly, for any array type or object A, and N an integer between 1 and the number of dimensions of A, the following attributes can be used:
| Attribute | Result |
| A'left(N) | Left bound of index range of dim'n N of A |
| A'right(N) | Right bound of index range of dim'n N of A |
| A'low(N) | Lower bound of index range of dim'n N of A |
| A'high(N) | Upper bound of index range of dim'n N of A |
| A'range(N) | Index range of dim'n N of A |
| A'reverse_range(N) | Reverse of index range of dim'n N of A |
| A'length(N) | Length of index range of dim'n N of A |