VHDL has an additional concurrent statement which can be used in architecture bodies to describe regular structures, such as arrays of blocks, component instances or processes. The syntax is:
generate_statement ::=
generate_label :
generation_scheme
generate
{
concurrent_statement }
end
generate [ generate_label ] ;
generation_scheme ::=
for generate_parameter_specification
| if condition
The for generation scheme describes structures which have a repeating pattern. The if generation scheme is usually used to handle exception cases within the structure, such as occur at the boundaries. This is best illustrated by example. Suppose we want to describe the structure of an adder constructed out of full-adder cells, with the exception of the least significant bit, which is consists of a half-adder. A generate statement to achieve this is shown in Figure 6-2.
adder : for i in 0 to width-1 generate
ls_bit : if i = 0 generate
ls_cell
: half_adder port map (a(0), b(0), sum(0), c_in(1));
end generate lsbit;
middle_bit : if i >
0 and i < width-1 generate
middle_cell
: full_adder port map (a(i), b(i), c_in(i), sum(i), c_in(i+1));
end generate middle_bit;
ms_bit : if i = width-1
generate
ms_cell
: full_adder port map (a(i), b(i), c_in(i), sum(i), carry);
end generate ms_bit;
end generate adder;
Figure 6-2. Generate statement for adder.
The outer generate statement iterates with i taking on values from 0 to width-1. For the least significant bit (i=0), an instance of a half adder component is generated. The input bits are connected to the least significant bits of a and b, the output bit is connected to the least significant bit of sum, and the carry bit is connectected to the carry in of the next stage. For intermediate bits, an instance of a full adder component is generated with inputs and outputs connected similarly to the first stage. For the most significant bit (i=width-1), an instance of the half adder is also generated, but its carry output bit is connected to the signal carry.