To illustrate the overall structure of a design description, a complete design file for the example in Section 1.4 is shown in Figure 5-6. The design file contains a number of design units which are analysed in order. The first design unit is the entity declaration of count2. Following it are two secondary units, architectures of the count2 entity. These must follow the entity declaration, as they are dependent on it. Next is another entity declaration, this being a test bench for the counter. It is followed by a secondary unit dependent on it, a structural description of the test bench. Following this is a configuration declaration for the test bench. It refers to the previously defined library units in the working library, so no library clause is needed. Notice that the count2 entity is referred to in the configuration as work.count2, using the library name. Lastly, there is a configuration declaration for the test bench using the structural architecture of count2. It uses two library units from a separate reference library, misc. Hence a library clause is included before the configuration declaration. The library units from this library are referred to in the configuration as misc.t_flipflop and misc.inverter.
This design description includes all of the design units in one file. It is equally possible to separate them into a number of files, with the opposite extreme being one design unit per file. If multiple files are used, you need to take care that you compile the files in the correct order, and re-compile dependent files if changes are made to one design unit. Source code control systems can be of use in automating this process.
-- primary unit: entity declaration of count2
entity count2 is
generic (prop_delay : Time := 10
ns);
port (clock : in bit;
q1,
q0 : out bit);
end count2;
-- secondary unit: a behavioural architecture body of count2
architecture behaviour of count2 is
begin
count_up: process (clock)
variable count_value : natural := 0;
begin
if
clock = '1' then
count_value
:= (count_value + 1) mod 4;
q0
<= bit'val(count_value mod 2) after prop_delay;
q1
<= bit'val(count_value / 2) after prop_delay;
end
if;
end process count_up;
end behaviour;
-- secondary unit: a structural architecture body of count2
architecture structure of count2 is
component t_flipflop
port
(ck : in bit; q : out bit);
end component;
component inverter
port
(a : in bit; y : out bit);
end component;
signal ff0, ff1, inv_ff0 : bit;
begin
bit_0 : t_flipflop port map (ck => clock, q => ff0);
inv : inverter port map (a => ff0, y => inv_ff0);
bit_1 : t_flipflop port map (ck => inv_ff0, q => ff1);
q0 <= ff0;
q1 <= ff1;
end structure;
-- primary unit: entity declaration of test bench
entity test_count2 is
end test_count2;
-- secondary unit: structural architecture body of test bench
architecture structure of test_count2 is
signal clock, q0, q1 : bit;
component count2
port
(clock : in bit;
q1,
q0 : out bit);
end component;
begin
counter : count2
port
map (clock => clock, q0 => q0, q1 => q1);
clock_driver : process
begin
clock
<= '0', '1' after 50 ns;
wait
for 100 ns;
end process clock_driver;
end structure;
-- primary unit: configuration using behavioural architecture
configuration test_count2_behaviour of test_count2 is
for structure -- of test_count2
for
counter : count2
use
entity work.count2(behaviour);
end
for;
end for;
end test_count2_behaviour;
-- primary unit: configuration using structural architecture
library misc;
configuration test_count2_structure of test_count2 is
for structure -- of test_count2
for
counter : count2
use
entity work.count2(structure);
for
structure -- of count_2
for
all : t_flipflop
use
entity misc.t_flipflop(behaviour);
end
for;
for
all : inverter
use
entity misc.inverter(behaviour);
end
for;
end
for;
end
for;
end for;
end test_count2_structure;
Figure 5-6 Complete design file