ABSTRACT

This paper describes a novel digital functional test sys­tem architecture in which the timing and waveform generation hardware work with a sequence of events in the same manner as an IC timing/logic simulator.

INTRODUCTION

As the complexity and pin count of VLSI integrated cir­cuits have exploded, test program generation has be­come immensely more complicated. VLSI semiconductor manufacturers are using the data from the simulation of these complex IC's to generate timing information and test vectors for the test program. In most cases either the input data to, or output data from the simulator must be modified, before timing and test vectors can be generated with this simulation data. This is primarily due to the difference in the technique in which the simulator and test systems handle wave-form generation.
Timing/logic simulators work with transitions in the in­put and output waveforms to the IC which are called events (i.e. event driven simulation). Test systems gen­erate waveforms by trying to fit a certain format around these transitions and then programming the time at which these transitions are to occur with edges from a timing generator. The IC simulation is not restricted to using formats or limiting the number of transitions that occur in a period of time. Often a simulation will con­tain waveforms that the test system can not produce. One solution is to perform a special simulation in which the input data to the simulator has been modified so that the simulation will not contain waveforms that can­not be produced on the test system. Another approach is to modify the simulation output to make the data fit the test system. Modifying the input or output of the simulation has several negative effects:

This paper introduces a new and novel ATE architec­ture, Sequencer Per Pin, in which waveforms are

generated in the same manner as a timing/logic simu­lator. We will describe how the Sequencer Per Pin architecture allows waveforms to be generated from the simulation data using an event sequence concept. Because this is the same concept as used by the sim­ulator no modifications are necessary to make the sim­ulation fit the test system architecture. This architecture reduces the test program generation time, while insuring that the intent of the simulation is per­formed during testing. The Sequencer Per Pin archi­tecture also makes generating hand coded test programs more straight forward and faster.

BACKGROUND

When digital functional automatic test equipment first became popular in the latter part of the 60's, its archi­tecture was very straightforward. Latches written by controllers formed the stimulus for the device under test, and comparators on the outputs would verify the device response. The standard paradigm for digital functional test was embedded in the ATLAS language statement "DO_DIGITAL_TEST", with the logical im­age of test functionality represented by the diagram of Figure 1.

The device is driven by FDrv if enabled by I/O. Other­wise the device output is compared to FExp as long as the signal Mask (or Strobe) permits. Each succeeding digital functional test consists of the following se­quence of events:

For each device pin, at any given instant in time at most one of the following state changes can occur:

Complexity arises because different pins require differ­ent sequences of events, and the timing at which the state changes are to occur will in general vary from pin to pin.
Test system architectures in the sixties and seventies evolved to minimize the hardware required to effective­ly produce large sequences of pin events. This was necessary, because good test hardware is costly. The principal architectural innovation of that period was the separation of functional data from timing, resulting in the development of very deep pattern memory applied with shared timing generators (TG's).[1] The functional data appeared as tables of 1's and O's (test vectors). Very effective functional tests could be produced for complex devices with just a few timing generators con­nected to pattern data by multiplexers and formatters. But this architectural construction, effective as it was at that time, introduced difficulties of its own. As devices became more complex, the process of parsing the test requirement into the pattern table and the timing be­came increasingly difficult. Limited numbers of timing resources inevitably imposed increasingly stringent re­strictions on their use. The translation from the simula­tor output to the test program became increasingly more obscure and problematical. At the same time, de­vice speeds dramatically increased, which made test margins ever more difficult to obtain. Pin skew and tim­ing generator distribution skew began to dominate tester performance considerations.[2]
During the last decade, TG-per-pin test systems were introduced to help alleviate some of these problems.[3-6] As more and more resources are applied indepen­dently to each of the device pins, fewer and fewer ma­chine restrictions are imposed on the functional test program. But simply applying a TG per pin does not eliminate the translation problem. The need to modify the simulation data exists regardless of whether the test system has shared resource timing or TG-per-pin timing architecture. The TG-per-pin architecture allows the flexibility to generate independent waveforms on

every device pin, but still restricts the waveforms with tester oriented formats and limited transitions. Further­more, many of the available TG-per-pin systems do not provide calibrated edge placement on all functions. Thus manual changes to the timing are still required to get adequate yields. These restrictions are removed by providing each pin with a full test event sequence ca­pability.

SEQUENCER PER PIN

We define an 'event' to be a pair (s,t), where 's' is a state and T is the time associated with a transition to 's'. An 'event sequence' is a time-ordered list of such pairs. For example, the waveform in Figure 2 here:

is defined by the event sequence (D1,1),(D0,8),(D1,13),(D0,18), interpreted as:

The seven event types identified earlier are sufficient to define any digital test completely. Clearly, such a list can be derived directly from a simulator output. The goal is to apply this simulator data directly to the de­vice. This goal is achieved simply by applying appropri­ate event sequences, as defined by the simulator output, to each pin independently. For this, we need a full sequencer for each pin. A Sequencer Per Pin cir­cuit contains the local memory, local memory address­ing, event timing generation, drive and strobe edge generation, event sequence memory, hardware cali­bration circuitry, strobe comparison, and fail storage logic. Each Sequencer Per Pin circuit is independent of all other pins.
For convenience in pattern storage and human com­prehension of the test sequence, we do not dispense with the concept of F-data entirely. Also to reduce the amount of storage allocated to time values, the con­cept of global test period is reintroduced. However, the global test period is no longer a statement of how fast the device is running; it becomes nothing more than a convenient method of subdividing the test. This results in the architecture shown in Figure 3.