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Тематическая статья №5

Ultra Low Power Design Techniques for FPGAs

Haris Akkool

http://www.fpgacentral.com

Power consumption is one of the most significant concerns apart from design complexity in FPGA design today. The concept of achieving System-On-Chip (SoC) functionality in an FPGA cuts down the design complexity yet power consumption is quickly becoming the most critical issue for the design community.

The world consumer electronics market is moving towards more portable products such as Portable Media Players (PMPs), MP3 Players, TV-On-Mobile, digital camera, camcorders, etc, where battery life is one of the most attractive design specifications for customers. Moreover, the requirement of lower power consumption increases drastically due to the encapsulation of electronic product without active cooling mechanism. Therefore, power reduction techniques must be considered during the design and component selection phase.

FPGA Power Components

There are four basic power components that need to be considered when selecting the appropriate FPGA technology for a low power application. They are Power Up or In-Rush power, Configuration power, Static power, and Dynamic power.

In-rush power: - During the startup stage, the device requires a substantial amount of logic array current for a specific duration in order to ramp up VDD to the correct voltage. This initial high current is called inrush current often seen as a power spike. The duration of VDD ramp up depend on the amount of current available from the power supply. When the VDD supply reaches 90 percent of its value, this initial high current is not required any longer.

Configuration Power: - The Configuration power is the power required to configure the device. This phase is typically required only for SRAM-based FPGAs where the configuration data for the device is stored in an external non-volatile memory such as an EPROM or Flash device. During configuration and initialization, the device draws current as the routing and look-up table (LUT) configurations are read from memory into the device, resets registers, enables I/O pins, and enters operating mode.

Static power: - The static power is proportional to the static current that flows when it is powered up, configured, and doing nothing, without activity at I/Os and clock inputs.

Dynamic Power: - Dynamic power is very sensitive to switched capacitances, mainly routing capacitances and it is a function of operating frequency and switching of capacitive loads, such as I/Os, internal gates, registers, clock lines, buffers, and internal memory accesses.

Technology and Device Selection

The technology selection is the first and most important step in low power design and it has a significant impact. There are mainly three types of FPGA technologies, interconnect, available such as Antifuse, SRAM and Flash.

Antifuse-based FPGAs consumes less static power than SRAM-based devices due to its Fine-Grained Architecture. The number of transistors requires for an SRAM-based FPGA is more than Antifuse-based FPGAs to implement equivalent functionality. This is due to the fact that SRAM-based FPGAs uses six-transistor SRAM cells to configure the interconnect and logic cells. Antifuse-based FPGAs do not require such transistors, and therefore draw orders of magnitude less power in static mode.

Antifuse FPGAs offer much lower dynamic power than SRAM-based FPGAs due to low switching capacitance and resistance of the antifuse element. Antifuse FPGAs can reduce the dynamic power consumption up to a factor of five when compared to the equivalent SRAM-based solution.

In addition to static and dynamic power, SRAM-based FPGAs have two more power component than Antifuse FPGAs such as in-rush power and configuration power.

So it is very clear that Antifuse FPGAs can offer ultra low power due to the architectural and interconnects features. Among the Antifuse FPGA vendors Quicklogic is the Market leader in supplying the lowest programmable solutions for this very same reason.

The anti-fuse technology implemented in QuickLogic devices is a proprietary technology called ViaLink. The ViaLink anti-fuse permits low routing capacitance and resistance enabling low overall power consumption and better performance than any other FPGA technology.

Quicklogic has recently released PolarPro FPGA family, with standby currents < 10 mA, to address applications that demand ultra-low power, small packaging, and high design security. PolarPro FPGAs exceed the functionality previously addressed by CPLDs and FPGAs with significant power and cost savings. PolarPro offers new and innovative logic cell architecture, versatile embedded memory with built-in FIFO control logic and advanced clock management control units.