Leshchenko Sergey

Faculty: Computer Science

Speciality "Computer Systems and Networks"

Development of methods and tools of detection and removal of failure test vectors in digital devices

Supervisor: Ph.D., Assistant Professor in the Department of Computer Engineering Zinchenko Yuriy

Abstract of the master's work

"Development of methods and tools of detection and removal of failure test vectors in digital devices"

Subject urgency

One of the basic problems at the synthesis of tests and especially at the pseudo-random generation is analysis of the failure states [7]. Partly this problem decides for some types of failures [6], in such systems as Pspice and their like, but many failure situations remain unrecognized.

The most complex object of diagnostics (OD), are known is asynchronous logic circuits [8]. In this work, as an alternative to the traditional approach the analysis of failure situations of asynchronous sequential circuits is invited to approach the analysis and removal races signals of triggers in CAD system ORCAD 10.0.

Due to the fact that the synthesis of tests for diagnostics of printed circuit boards(PCB) the main problem consists in the analysis of the failure states are relevant studies on the generation of correct test vectors through the construction of traps to avoid failure situations [9].

Purposes and tasks

The purpose of work is a generation of pseudo-random tests for digital model elements of sub (MES), containing no bad sites. To achieve this goal in the work the following objectives :

• development algorithm of search triggers of digital devices (DD), based on the original description of OD in the general level and in the format EDIF;
• construction of logical models for each trigger and including them in the general model of OD;
• develop analysis subsystem failure situations MES based CAD system ORCAD using description language analog-digital devices PSpice;
• experimental studies of test constructions MES with the use of CAD-tests Adaptive PRTG-LAN and subsystem analysis of failure situations.

Scientific novelty and practical results

The work presents approach analysis of failure situations DD by the design OD together with the models of logical trap failures.

The realized subsystem analysis of failure situations of MES can be used :

• as a synthesis of the correct test vectors;
• in the educational process in carrying out laboratory works;
• enterprises that are engaged in constructing tests for the MES.

Approbation

The work were reported on international scientific conferences for students, graduate students and young scientists "Information and computer technologies — 2009" (section "Design of computer and digital devices, FPGA-technology").

The main content

Mathematical modeling as a method of automated planning of computing devices

The most effective way to study of capacity of complex computational device is modeling. The basic methods of automated research performance of computing devices are the following :

• breadboarding;
• physical modeling;
• analytical modeling;
• mathematic modeling.

The method of simulation on a computer supposes to use as the object of debugging a program model designed system. This method is universal, because the model can be got for the computer system of any structure and architecture. The most common method of planning is a mathematical simulation.

Modern CAD systems such as OrCAD-10.0, PCAD-2006, MicroSIM, MicroCAP allow to perform modeling of analog-digital devices in a single session. To simulate the analog part of the device used techniques associated with the solution of ordinary differential equations, while for digital part using methods, oriented on modeling of stationary processes on the level of stable states of a logical "zero" and logical "one".

Using the logic modeling in schematic planning of computing devices

The most widespread way to study the performance of simulated digital devices is a logical simulation. The main task of logical modeling is to assess the quality of the proposed variant of the functional circuit of the designed device. The first phase investigated the scheme to meet the specified functions without delay signals, limitations of element base and external terms. Similar verification does not require much computer time and allows you to identify errors in the structure of the device, made during its synthesis. Phase II study is testing of the device taking into account the delays of elements constituting its structure and effects of various destabilizing factors. This analysis makes it possible to identify the critical hazards encountered in asynchronous circuits [10].

It is known that the modeling of complex devices, there is always the danger of a temporary mismatch between input elements, which can result a false signal at the output of the logical element — dynamic and static failure hazard [5]. Different CAD depending on the methods of design indicate a different appearance of such a situation. Thus the binary modeling techniques are ineffective in the analysis of not only dynamic but also static failure hazard. In CAD, which implemented the use of multi-valued models for representation of signals of the first type, is performed only indication of failure.

Failure states analysis on the basis of PSpice-model

The idea proposed approach can be described using the "model of generating the correct pseudo-random tests" (fig. 1).

Figure 1 — General circuit of the software diagnostics PCB (Animation: volume — 32 KB; size — 360x335, the number of frames — 3, the delay between frames — 1 s, the delay between the first and last frames — 3 s, the number of cycles of repetition — infinity.)

The scheme includes the generator of random or pseudo-random tests [11], object of diagnostics (PSpice-model) and scheme of analysis failure vectors. The generator of pseudo-random tests generates the pseudo-random sequence of input signals. The values of the generated signals are given on a PSpice-model which defines “correct” " the filing of such a combination. In the case of failure situation on the generator of pseudo-random test is served a signal back to a few iteraciy iterations for a subsequent modeling. The scheme of analysis of failure vectors used to detect of failure situations, missed the software environment for diagnostics of the PCB.

The scheme of analysis of failure vectors calculates the error signal E1 to return the simulation stage to the previous step, the signal E2, which allows you to continue the simulation in the case of special situations.

Thus, this scheme makes it possible to intercept failure vector signals, which does not recognize the model used PSpice, which excludes the appearance of incorrect input vectors in random test generation.

Review of failures in asynchronous sequential circuits

In the scheme of analysis of failure vectors of trap are built in accordance with the triggers on the basis of CAD-data of OD in CAD system ORCAD 10.0.The general scheme of the trigger, which may arise race signals, is presented in Figure 2.

Figure 2 — Block diagram of RS-trigger

Analysis of failure situation occurs on the basis of external influences on the circuit inputs.As a result, built a trap failure, which in the case of "incorrect" combination forms the signals E1 and E2, which causes a return to a few iterations for subsequent modeling.

The races of signals begins in the case of transition from the forbidden combination in storage mode. Trap catches such situation and generates the control action on the generator of pseudorandom tests.

Conclusion

Thus in this work were considered the main ways of automated research performance computing devices. To this moment the program of construction traps is debugged and work is underway to appoint temporary delay circuit traps according delays chip OD.

References

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Note

The master’s work has not completed yet. Completion date is December 2010. Full text can be received from the author or his scientific advisor after this date.