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Українська
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Masters' portal
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DonNTU site
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Alexander Sherekin
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Abstract of Master's thesis
System-on-Chip Verification based on Boundary Scan |
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| Brief contents | |
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| Relevance of the work | |
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The process of developing systems-on-chip (SoC) is long and complex. It requires the efforts of a large number of people, who design both hardware and software of the SoC. Occurrence of errors has a high probability because significant number of designers are involved into this process. Because of it the verification step is added to the production process. Verification and testing is in the amount of about 60% of the total design time, which proves their importance [1]. Today's pace of technology development requires similar tempos of development of verification and testing methods. One of the most popular method of verification was the guide probe method, when an analyzer, probe, was moving from one side of scheme to the other and analyzed the values in different parts of the scheme. During this moving, it made a conclusion about the presence or absence of faults. This method can easily be applied to small and medium integrated circuits (IC). Density of elements in IC has increased very quickly. So direct access to all necessary points of the scheme for the analysis was not possible. It led to the need to find radically new way of verification. And it was found in 1990. It was the standard IEEE 1149.1-1990 Boundary Scan (BS) [2]. The main function of BS was to test interconnects of IC and logic blocks within these schemes. But BS also was usable for performing the verification, testing and debugging, because it provided the opportunity to display out the scheme and observe the internal signals of the circuit. |
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| Analysis of problem | |
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The main part of BS technology is build-in scheme. It usually builds into the project. This scheme consists of the following elements [3]:
Together with BS was created the description language of BS-structures (BSDL — Boundary Scan Description Language). This language is used for computer-oriented description of the structure of the BS selected IP and features of this particular structure. Files written in this language used in automatic test generators [4]. BSDL-add-in can be automatically added to the project at various stages of its existence: before synthesis or after. Considering the BS-verification products and tools, provided by Xilinx, it should be noted the system Chip Scope Pro, which includes:
The most important IP-core members of the BSDL-structure are ICON, ILA, and VIO. ICON provides the interface between the BS-component system on the FPGA and Chip Scope Pro. ICON allows you to connect IP-core, such as the ILA, VIO. Amount of cores, which can be attached to one ICON, is 15 or less [5]. ILA — configurable logic analyzer, which is used to monitor the state of internal signals of verifiable scheme. ILA has 16 trigger ports, each of which consists of a maximum 256 signals (this count is customizable). The process of obtaining and storing data from the circuit begins automatically when you start the core. But the moment of start can be configured as desired. The condition for starting the kernel can be any logic function, which consists of the signals connected to the scheme. As soon as the specified function will be set to true, all the signals of the analyzed schemes will begin to store into the internal RAM ILA. Then all this signals pass the ICON and the JTAG port to the computer and can be displayed in the Chip Scope. Figure 1 shows the connection of ILA and ICON [6]. 
Figure 1 — ILA and ICON connection 
Figure 2 — VIO and ICON connection We have reviewed the tools which are used for verification and testing projects based-on FPGAs from Xilinx. Now we must also determine the place of verification in the overall design process. The first phase of design creates a behavioral model based on the specifications of the project. It is modeled and verified. Then it is synthesized. Apart from this, you create a new model in the structural, or the register (RTL — Register Transfer Level), style. At the next step we perform the comparison of two models, the behavioral and RTL. If the model works differently, we must correct an RTL model as long as the work of both models will not be identical. Then we generate tests that cover the maximum number of possible errors. At this stage it is necessary to make a choice of verification and test generation algorithm. Upon completion of the formation of test inputs and modeling, we apply them to the basic scheme and analyze it's error-coverage. If it does not satisfy the requirements of the project, we either choose another method of verification, or increase the number of tests. When this process is complete, we implement the synthesized model into FPGA. Then we test it and check whether the results of the real scheme are the same as they were in basic model. |
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| Goals and Objectives | |
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The aim of this work is to develop a method of verification of system-on-chip based-on Field Programmable Gate Array (FPGA). The scheme will comply with the above-described structure of the design, but more specifically disclose the nature of each phase and to optimize and facilitate the process of testing and verification. The developed scheme should take into account the peculiarities of the technology Boundary Scan and verification tools from Xilinx and use effectively all their dignity. With the help of the developed structure we must to show the entire verification process on the example of a particular device. |
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| A review of research and development | |
| Materials of DonNTU Masters | |
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| National level | |
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At the web-site of my supervisor Hard Club you can learn about the scientific works in subjects close to master's one. |
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| Global level | |
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The master's work theme is, on the one hand, actual in the world, but on the other hand, the bulk of the works on the subject are not available in the public domain. Access is granted only to brief reviews of articles. Among the small number of available materials attention should be paid to the publication [8] and [9]. The first of these publications describes an improved structure of BS-registers, which saves space on the chip by reducing the number of internal registers, and speeds up the BS, by paralleling the process of data exchange. The second publication describes a new method for detecting faults in the PLD (Programmable Logic Device) and FPGA, using the technology of BS. From Russian sources the paper [10] should be considered. The modern means of functional verification are described in this article. |
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| The results obtained at the time of writing the abstract | |
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At the moment, the verification structure has been developed. According to it further verification of the project will be carried out. This structure can be divided into several parts / phases of the verification:
Advantages of this approach are in a small amount of traffic, passed between the FPGA and PC. Disadvantage is an inability to replace the bug searching algorithm easily, because it is hardcoded in the FPGA. If you want to replace it is necessary to flash FPGA again. But on the other hand, flashing is not a complicated process that allows you to talk about the structure as a recommended for use. |
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| Literature | |
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| Master's work is not yet complete during writing this essay. Final completion: December 2012. The full text of the work and materials on the topic can be obtained from the author or his supervisor after that date. | |