Actuality of research theme :

Stormy development of modern integral microcircuitry, especially programmable logical integrated circuits (PLIC), resulted in that widely widespread algebraic methodology of the logical planning of digital devices left off to ripen after technological progress. Changeability of base demanded development of all new algebraic methods.

Degree of scientific character :

Development ptimization methods of managing automat using technology mapping, as method of decouplig is inalienable part of scientific research , which in future allow to considerably shorten device expenses during realization.

Purpose and tasks of dissertation research :

Purpose of technology mapping, as a method of decomposition to shorten in-use space, delay, or combination both ways in the network of programmable logical blocks. Main task, which we put in this work , to estimate modern algorithms technologies of FPGA technology mapping and develop own algorithms and methods from point of optimization occupied space.

Research object:

Managing Moore automaton and FPGA components : combination logical blocks ( С LB), co-operation between them, and also boolean functions and their optimization from point of the occupied space on the chip .

Article of research :

Realization of algorithms, which optimize boolean functions in PLIC (FPGA).

Research area :

Research optimization methods of managing automats in basis of standard large-scale integrated circuits.

Theoretical and methodological bases of research :

Research |work-up| of associate professor Zelenevoy I. J . « O ptimization Algorithms of managing automats ». Results of researches in technology mapping optimization of the occupied space C LB . (university of Toronto).

  Scientific novelty:

 

Substantive provisions and results, sustained on research

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The re-configurable integrated circuits (FPGA) are programmable logical blocks, surrounded configurable interconnection wirings . The most modern devices of FPGA are contained programmable logical blocks, based on K-input LUT (K-LUT ), each K-LUT contains 2^K configured bits. By the instrumentality of this bits any K-input function will be realized .

The number of LUTs , necessary for realization of the given circuit, determines a size and cost of FPGA realization. Therefore one of the main steps of the automated FPGA engineering is drawing a map, which carries description of logical circuit on scores LUTs of FPGA architecture.

Purpose of technology mapping, as decouplig method - to shorten in-use space, delay, or combination that et al in the network of programmable logical blocks. In this work modern technologies algorithms of plotting are estimated on a map from point of occupied space optimization.

Further researches are related to realization of control units on FPGA and further logical circuit optimization on cost descriptions. Researches are directed on confirmation (or refutation) of theoretical suppositions that optimum transformation of subcharts allows to utillize less of LUTs, thus total |sum-total| optimization of the occupied space can arrive about 60%, that substantially influences on diminishing of total cost of device.

List of works published on the topic