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Chernysh Igor

Chernysh Igor

Faculty: Computer sciences and technologies
Departmen: Ñomputer engineering

Theme of master's work:

Research of structures of composition firmware control units with the general adressing in the basis of standard LIS

Scientific adviser: Zelenyova Irina

About author

Summary of research and developments

Introduction (Motivation)

Nowadays there are a powerful tendency toward development of web technologies. One of the main tasks of this direction is a transfer of function blocks of processing to a server, and also maximal simplification of man-machine interface [24, 25]. As a result an user gets the system, in which simple commands become investigation of implementation of difficult algorithms, which requires the expenses of greater amount of resources. These expenses are fully carried on a server, that practically does not tell on the resources of the personal computer. Java Applet is used to provide the interactive possibilities of web applications, which can not be given by HTML [24, 25]. Because byte-code of Java isn’t dependent on any platform, Java Applet can be executed by the plagins of the browsers of many platforms, including Microsoft Windows, UNIX, Apple Mac OS and GNU/Linux. Such programs with the opened source code, as applet2app, can be used to transform the applet to the independent programs on Java or executable files of Linux and Windows [24, 25].

On account of the presence of great number of the operating systems, there is a problem to create application, working on any of them. Consequently, in the decision of task it is necessary to obtain crossplatform.

The structures of control units are concidered in this work as a subject domain. One of methods of realization of control unit of the digital system is the use of model of composition microprogrammed control unit (CMCU) [26, 27].

Survey of research and developments

A research task for our project consists in determination of the most optimum managing automat for realization of the set algorithm. An algorithm is set as graphic scheme (GSA). A man-machine interface contains all graphic components, from which in the process of computing GSA is built. Parallell with this process XML-file is generated, containing information about an algorithm(number of operated and conditional tops, structure of GSA) which in the total is sent to a server. On a server in accordance with statistics in a database is executed the analysis of XML-file and a managing automat most suitable for realization of the user’s algorithm is chosen. In reply from a server user gets reference on VHDL. It is a file, being the model of the chosen type.

For interpretation of GSA G it is possible to use CMCU model with general memory [27]. (Pic.1).

Pic.1 — Structure scheme of CMCU with general memory.

This device functions according to the following scheme. On the Start signal a zero address of first microcommand of microprogramme is loaded in the scaler of ST, proper to GSA G. At the same time trigger of fetch of TF is set in the single states (Fetch=1). Next microcommand (MC) gets out from control storage of ÑÌ. If this MC corresponds the top of bq Og, simultaneously with the set of microoperations of Y(bq) the variable of y0=1 is formed. If y0=1, content of ST is increased on 1, on the signal of Clock it corresponds the mode (3), it means that transition takes place into some statement linear chain (SLC) g Ñ. If bq=Og, variable of y0=0. In this case the combinational circuit of ÑÑ forms the functions of excitation of CT.

F=F(T,X) necessary for a load in ST the address of entrance of some SLC. The address is set in ST on the signal of Clock. If , where bE — is an eventual top of GSA G, the variable of yE=1 is formed. If yE=1, trigger of TF is set in a zero state (Fetch=0). In this case the selection of microcommands from ÑÌ is halted and CMCU U1 is halted.

Obviously, this CMUU is an automat of Mur, as output signals y0, yE è Y depend only from content of ÑÒ. Herewith the address of microcommand can be treated as the code of the state of automat. However in a difference from a classic automat of Mur, memory of CMCU is realized on a scaler.

Main planned results

The example of synthesis of CMCU on GSA G1 (Pic.2)

Pic.2 — Initial GSA G1

Using methods from [4], it is possible to get the great number of Ñ={²1, ²2, ²3}, where d1= I =b1, I =O1=b2; ²2=, I =b3, I =b4, O2=b5; Î3==, I =b6, O3=b8. So, G=3, M=8, R=3, T={T1, T2, T3}, D={D1, D2, D3}, X={x1, x2}, L=2, Y={y1, y2, y3, y4, y5, y6}, N=6, I( )={b1, b2, b3, b4,b6}, O( )={b2, b5, b8}, C1={c1, c2}.

The natural adressing of microcommands [27] allows to get the followings addresses: A(b1)=000, A(b2)=001, …, A(b8)=111. Transition formulas are built for the outputs of SLC. This system has the following view: O1 > x1 b3 x2 b4 b6;

The system has H=4 of therm, consequently, the table of jumps of KMCU has H=4 lines (Tabl.1).

Table 1 — table of jumps of KMCU

Content of control storage of CMCU is shown in Tabl.2, having M=8 lines.

Table 2 — Content of control storage of CMMU

On the next step of doing sums the XML file, which contains information on initial GSA, is being formed. Content of XML file is shown on picture 3.

Pic.3 — Content of XML-file

On a next step this file is sent to the server. On the server in accordance with statistics in the database the XML-file is analized and control automat, most suitable for realization of the algorithm, offered by user, is chosen. In reply from the server user gets reference to VHDL-file, which is the model of most suitable.

Development process MA on PLIS represented on a picture 4

Pic.4 — is development process MA on PLIS

Animation: 8 frames, weight — 47492 bytes, size — 760x241

Conclusions and future research

As a result of doing sums VHDL file and statistics are created, on which it is possible to define graphically the most optimum architectures of UA for realization of control algorithms, set by user. Because applications realized on java with the use of technology of Java Applet, in total crossplatform application is created, i.e. application, working in any operating system.

References

    Works master's degrees of past yesar

  1. Áåðåæîê Alex George:
  2. Borovlev Artem Sergey:
  3. VoytenkoSergey Arkad'evich:
  4. DanilovMaksim Vasiliy:
  5. KostyanokTyat'yana Nick:
  6. Siluanov Anton Feodor:
  7. Skoropad Alexander Sergey:
  8. Cololo Sergey Alex:
  9. Shishko Sergey Nick:

    Universities of Ukrainy

  10. Vostochnoukrainsk national university the name of V.Dalya
  11. Dnepropetrovsk national university
  12. Doneck state institute of artificial intelligence
  13. Zaporozhsk state engineering academy
  14. National aviation university
  15. Khar'kovskiy national university of radio electronics

    Foreign research

  16. University Augzburga
  17. Faculty of computer sciences of the Drezdenskogo technical university
  18. Laboratory control the system Karlsrue university (Germany)
  19. Israel association of automatic control (IAAC)
  20. Center research of the complex automated systems (Bolonskiy university, Italy)
  21. Zelenogursk university (Poland)
  22. Vladimir state university
  23. Moscow State Institute of Electronic Technique

    Printing sources

  24. Key With. Khorstman, Harry Kornell "Java 2. Library of professional";
  25. G. Shildt the "Complete reference book on Java";
  26. BarkalovA.A. Mikroprogrammnoe control unit as composition of automats with programmable and hard logic. Automation and computing engineering, 1983, ?4.-n.36-41.
  27. Barkalov A.A., Titarenko L.A. Synthesis of operational and control automate. — Donets’ñ: Untech, 2005.-25pp.
  28. Maxfield C. The Design Warrior’s Guide for FPGA.-Amsterdam: Elsevier, 2004.-541 p.
  29. Smith M. Application – Specific Integrated Circuits. — Boston: Addison — Wesley, 1997. — 836 pp.
  30. Baranov S. Logic Synthesis for Control Automate. — Boston: Kluwer Academic Publishers, 1984.-312pp.

About autor